參數(shù)資料
型號(hào): MT16LSDT6464AI
廠商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM MODULE
中文描述: 同步DRAM模塊
文件頁(yè)數(shù): 11/24頁(yè)
文件大?。?/td> 614K
代理商: MT16LSDT6464AI
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
11
2002, Micron Technology Inc.
Commands
The Truth Table provides a quick reference of avail-
able commands. This is followed by written descrip-
tion of each command. For a more detailed descrip-
tion of commands and operations, refer to the 256Mb
SDRAM component data sheet.
NOTE:
1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW dis-
ables the auto-precharge feature; BA0-BA1 determine which device bank is being read from or written to.
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged
and BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 9:
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table
Truth Table – SDRAM Commands and DQMB Operation
NAME (FUNCTION)
CS#
RAS# CAS#
WE#
DQMB
ADDR
DQ
NOTES
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE
burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
H
L
L
L
L
X
H
L
H
H
X
H
H
L
L
X
H
H
H
L
X
X
X
X
X
X
X
X
X
Bank/Row
Bank/Col
Bank/Col
1
2
2
L/H
L/H
Valid
L
L
L
H
L
L
H
H
L
L
L
H
X
X
X
X
Active
X
X
Code
X
3
4, 5
L
L
L
L
X
L
H
Op-code
X
6
7
7
Active
High-Z
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