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參數資料
| 型號： | MT16LSDT6464AG-13E |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM MODULE |
| 中文描述： | 同步DRAM模塊 |
| 文件頁數： | 10/24頁 |
| 文件大小： | 614K |
| 代理商： | MT16LSDT6464AG-13E |
256MB / 512MB (x64)
168-PIN SDRAM DIMMs
32,64 Meg x 64 SDRAM DIMMs
SD8_16C32_64x64AG_C.fm - Rev. C 11/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
10
2002, Micron Technology Inc.
CAS Latency
The CAS latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
If a READ command is registered at clock edge
n
,
and the latency is
m
clocks, the data will be available
by clock edge
n
+
m
. The DQs will start driving as a
result of the clock edge one cycle earlier (
n
+
m
- 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 6, CAS Latency
Diagram. Table 8, CAS Latency Table, indicates the
operating frequencies at which each CAS latency set-
ting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Figure 6: CAS Latency Diagram
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0–
M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
t
D
OUT
tOH
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
t
D
OUT
tOH
COMMAND
NOP
READ
tAC
NOP
Table 8:
CAS Latency Table
ALLOWABLE OPERATING
CLOCK FREQUENCY (MHZ)
SPEED
CAS LATENCY = 2
CAS LATENCY = 3
-13E
-133
-10E
133
100
100
143
133
NA
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