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參數資料
| 型號： | MSP50C614PJM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | 0-BIT, 12.32 MHz, MIXED DSP, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 122K |
| 代理商： | MSP50C614PJM |
MSP50C614
MIXED-SIGNAL PROCESSOR
SPSS023C – DECEMBER 1999 – REVISED FEBRUARY 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Advanced, Integrated Speech Synthesizer
for High-Quality Sound.
D Operates up to 12.32 MHz (Performs up to
12 MIPS)
D Single-Chip Solution for up to 6.8 Minutes
of Speech
D External ROM Interface for up to 18.8 Hours
of Speech
D Supports High-Quality Synthesis
Algorithms Such as MELP, CELP, LPC,
ADPCM, and Polyphonic Music
D Simultaneous Speech Plus Music
Capability
D Very Low-Power Operation, Ideal for
Hand-Held Devices.
D Low-Voltage Operation, Sustainable by
Three Batteries
D Reduced Power Stand-By Modes, Less
Than 10
A in Deep-Sleep Mode
D Contains 64K Byte Words Onboard ROM
(2K Words Reserved)
D 640-Word RAM
D 64 I/O Pins Consisting of
– 40 General-Purpose Bit Configurable I/O
– 8 Inputs With Programmable Pullup
Resistor and Dedicated Interrupt
(Key-Scan)
– 16 Dedicated Output Pins
D Direct Speaker Driver, 32 (PDM)
D One-bit Comparator With Edge-Detection
Interrupt Service
D Resistor-Trimmed Oscillator or 32.768 kHz
Crystal Reference Oscillator
D Serial Scan Port for In-Circuit Emulation
and Diagnostics
D The MSP50C614 Is Sold in Die Form, or
100-pin PJM Package
D An Emulator Device Is Available in a
Ceramic Package for Development
description
The MSP50C614 is a low-cost, mixed-signal processor that combines a speech synthesizer, general-purpose
I/O, onboard ROM, and direct speaker-drive in a single package. The computational unit utilizes a powerful new
DSP which gives the MSP50C614 unprecedented speed and computational flexibility compared with previous
devices of its type. The MSP50C614 supports a variety of speech and audio coding algorithms, providing a
range of options with respect to speech duration and sound quality.
The device consists of a micro-DSP core, embedded program, and data memory, and a self-contained clock
generation system. General-purpose periphery is comprised of 64 bits of partially configurable I/O.
The core processor is a general-purpose 16-bit microcontroller with DSP capability. The basic core block
includes computational unit (CU), data address unit, program address unit, two timers, eight level interrupt
processor, and several system and control registers. The core processor gives the MSP50C614 break-point
capability in emulation.
The processor is Harvard type for efficient DSP algorithm execution. It requires separate program and data
memory blocks to permit simultaneous access. It is configured in 32K 17-bit words.
The total ROM space is divided into two areas: 1) The lower 2K words are reserved by Texas Instruments for
the purposes of a built-in self-test 2) The upper 30K is for user program/data.
The data memory is internal static RAM. The RAM is configured in 640 17-bit words. Both memories are
designed to consume minimum power at a given system clock and algorithm acquisition frequency.
Copyright
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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