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MSP430F551x
MSP430F552x
SLAS590E
– MARCH 2009 – REVISED APRIL 2011
TB0
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 17. TB0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE
MODULE
DEVICE
MODULE
INPUT
OUTPUT
RGC/YFF/
BLOCK
PN
RGC/YFF/ZQE(1)
PN
SIGNAL
ZQE(1)
60-P7.7
TB0CLK
TBCLK
ACLK
(internal)
Timer
NA
SMCLK
(internal)
60-P7.7
TB0CLK
TBCLK
55-P5.6
TB0.0
CCI0A
55-P5.6
ADC12
(internal)(2)
55-P5.6
TB0.0
CCI0B
ADC12SHSx =
CCR0
TB0
TB0.0
{2}
DVSS
GND
DVCC
VCC
56-P5.7
TB0.1
CCI1A
56-P5.7
ADC12 (internal)
CBOUT
CCI1B
ADC12SHSx =
(internal)
CCR1
TB1
TB0.1
{3}
DVSS
GND
DVCC
VCC
57-P7.4
TB0.2
CCI2A
57-P7.4
TB0.2
CCI2B
CCR2
TB2
TB0.2
DVSS
GND
DVCC
VCC
58-P7.5
TB0.3
CCI3A
58-P7.5
TB0.3
CCI3B
CCR3
TB3
TB0.3
DVSS
GND
DVCC
VCC
59-P7.6
TB0.4
CCI4A
59-P7.6
TB0.4
CCI4B
CCR4
TB4
TB0.4
DVSS
GND
DVCC
VCC
42-P3.5
TB0.5
CCI5A
42-P3.5
TB0.5
CCI5B
CCR5
TB5
TB0.5
DVSS
GND
DVCC
VCC
43-P3.6
TB0.6
CCI6A
43-P3.6
ACLK
CCI6B
(internal)
CCR6
TB6
TB0.6
DVSS
GND
DVCC
VCC
(1)
Timer functions selectable via the port mapping controller.
(2)
Only on devices with ADC.
Copyright
2009–2011, Texas Instruments Incorporated
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