參數(shù)資料
型號： MSP430F423IPMR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, QFP-64
文件頁數(shù)： 11/45頁
文件大小： 917K
代理商： MSP430F423IPMR
MSP430F42x
MIXED SIGNAL MICROCONTROLLER
SLAS421A APRIL 2004 REVISED JUNE 2007
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Schmitt-trigger inputs Ports P1 and P2; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIT+
Positive-going input threshold voltage
VCC = 3 V
1.5
1.98
V
VIT
Negative-going input threshold voltage
VCC = 3 V
0.9
1.3
V
Vhys
Input voltage hysteresis (VIT+ VIT)
VCC = 3 V
0.45
1
V
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
t
External interrupt timing
Port P1, P2: P1.x to P2.x, External trigger signal
3 V
1.5
cycle
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)
3 V
50
ns
t(cap)
Timer_A, capture timing
TAx
3 V
50
ns
f(TAext)
Timer_A clock frequency
externally applied to pin
TACLK, INCLK t(H) = t(L)
3 V
10
MHz
f(TAint)
Timer_A clock frequency
SMCLK or ACLK signal selected
3 V
10
MHz
NOTES:
1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Ilkg(P1.x)
Leakage
Port P1
Port 1: V(P1.x) (see Note 2)
V
=3V
±50
nA
Ilkg(P2.x)
Leakage
current
Port P2
Port 2: V(P2.x) (see Note 2)
VCC = 3 V
±50
nA
NOTES:
1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as an input.
outputs Ports P1 and P2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
High level output voltage
IOH(max) = 1.5 mA,
VCC = 3 V,
See Note 1
VCC0.25
VCC
V
VOH
High-level output voltage
IOH(max) = 6 mA,
VCC = 3 V,
See Note 2
VCC0.6
VCC
V
Low level output voltage
IOL(max) = 1.5 mA,
VCC = 3 V,
See Note 1
VSS
VSS+0.25
V
VOL
Low-level output voltage
IOL(max) = 6 mA,
VCC = 3 V,
See Note 2
VSS
VSS+0.6
V
NOTES:
1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the
maximum specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the
maximum specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fPx.y
(1
≤ x ≤ 2, 0 ≤ y ≤ 7)
CL = 20 pF,
IL = ± 1.5mA
VCC = 3 V
DC
12
MHz
fACLK,
fMCLK,
fSMCLK
P1.1/TA0/MCLK
P1.5/TACLK/ACLK/S28
CL = 20 pF
VCC = 3 V
12
MHz
P1.5/TACLK/ACLK/
fACLK = fLFXT1 = fXT1
40%
60%
P1.5/TACLK/ACLK/
S28, CL = 20 pF
fACLK = fLFXT1 = fLF
30%
70%
tXdc
Duty cycle of output frequency
S28, CL
20 pF
VCC = 3 V
fACLK = fLFXT1
50%
tXdc
Duty cycle of output frequency
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 3 V
fMCLK = fDCOCLK
50%
15 ns
50%
50%+
15 ns
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