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| 型號(hào)： | MSM9225GA-2K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44 |
| 封裝： | 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 53/74頁(yè) |
| 文件大小： | 487K |
| 代理商： | MSM9225GA-2K |
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Semiconductor
MSM9225
57/73
(4) Error states
(a) Types of error states
There are three types of error states: error active, error passive, and bus OFF.
Error states are managed by the transmit error counter and the receive error counter.
Each error state is classified according to the error counter value.
The error flag that is output differs depending upon whether the error state is a transmit or
receive operation
If the value of the error counter is 96 or greater, the bus may be heavily damaged. The bus must
be tested for this condition.
If only one node is active at startup, even if data is transmit an Ack will not be returned.
Therefore, error frame and data retransmission are repeated. In this case, the bus OFF state will
not be entered. Even if an error state is repeated at the node that transmits messages, the bus
OFF state will not be entered.
After reset and after the sleep mode wakes up, the error passive state continues until Ack is
received. Regardless of the number of errors that occur, the transmit error counter will be 255.
Reception can be performed even if transmission is in the bus OFF state.
Type of error state
Operation
Error counter value
Type of error flag to be output
Error active
Transmit/Receive
from 0 to 127
Active error flag
(6 consecutive "dominant" bits)
Error passive
Transmit
from 128 to 255
Passive error flag
(6 consecutive "recessive" bits)
Bus OFF
Transmit
256 or greater
Communication not possible.
If 11 consecutive "recessive" bits occur 128
times, then when the error counter = 0, the
state can return to error active.
Receive
128 or greater
Receive
—
No bus OFF
(b) Error counter
The error counter is incremented when errors occur and is decremented when transmission or
reception is performed correctly. Timing of the increment or decrement occurs at the 1st bit of
the error flag.
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