參數(shù)資料
型號(hào)： MSM9225GA-2K
廠(chǎng)商： OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PQFP44
封裝： 9 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-44
文件頁(yè)數(shù)： 11/74頁(yè)
文件大?。?/td> 487K
代理商： MSM9225GA-2K
Semiconductor
MSM9225
19/73
If setting is :
BTR0 = "01000001" ...SJWB = "0" SJWA = "1" BRP5-0 = "000001"
BTR1 = "00000001"...TSEG2 = "000" TSEG1 = "0001"
then the bit timing is as follows
Sync segment
1 BTL cycle (fixed)
SJW 1
2 BTL cycle
TSEG 1
2 BTL cycle
TSEG 2
1 BTL cycle
SJW 2
2 BTL cycle
1 bit time
8 BTL cycle
Sampling point = 5 BTL cycle
If fosc = 16 MHz, then 1 BTL cycle is :
BTL cycle = 2 (25 0 + 24 0 + 23 0 + 22 0 + 21 0 + 1 + 1) / 16 MHz = 0.25 ms
Therefore 1 bit time is :
8 BTL cycle = 8 0.25 ms = 2.0 ms
(= 500 Kb/s)
6. Communication input/output control register (TIOC: 2Fhex)
This register sets the communication mode and output buffer format.
Writing to the TIOC bit is enabled, when the INIT bit of the CAN control register (CANC:
0Ehex) is "1".
The bit configuration is as follows:
(3) Bit timing
Bit timing is set by CAN bus timing registers 0 and 1. The relationship between 1 bit time
of a message and a CAN bus timing (the MSM9225 register) is as follows:
1 bit time
SJW1
(BTR0 : SJWB/A)
TSEG1
(BTR1 : TSEG13-10)
TSEG2
(BTR1 : TSEG22-20)
SJW2
(= SJW1)
1BTL
cycle
Sampling
point
PROP-SEG
SYNC-SEG
PHASE-SEG1
PHASE-SEG2
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