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參數資料
| 型號： | MSC8112TVT2400V |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 32/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | DSP DUAL CORE 431-FCPBGA |
| 標準包裝： | 60 |
| 系列： | StarCore |
| 類型： | SC140 內核 |
| 接口： | 以太網，I²C，TDM，UART |
| 時鐘速率： | 300MHz |
| 非易失內存： | 外部 |
| 芯片上RAM： | 448kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 1.10V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 431-BFBGA，FCBGA |
| 供應商設備封裝： | 431-FCPBGA（20x20） |
| 包裝： | 托盤 |
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MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Hardware Design Considerations
Freescale Semiconductor
38
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in
Figure 34. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-F capacitor should be closest
to VCCSYN, followed by the 10-F capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be
kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN
by a 0.01-F capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8112 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
3.3
Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to the non-active value, via resistors to
VDDH or GND, except for the following:
If the DSI is unused (DDR[DSIDIS] is set), HCS and HBCS must pulled up and all the rest of the DSI signals can be
disconnected.
When the DSI uses synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either
up or down, depending on design requirements.
HDST
can be disconnected if the DSI is in big-endian mode, or if the DSI is in little-endian mode and the
DCR[DSRFA] bit is set.
When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, pull up HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/
HDBE[1–3]
and HWBS[4–7]/HDBS[4–7]/HWBE[4–7]/HDBE[4–7]/PWE[4–7]/PSDDQM[4–7]/PBS[4–7].
When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1–3]/HDBS[1–3]/HWBE[1–3]/HDBE[1–3]
must be pulled up.
When the DSI is in asynchronous mode, HBRST and HCLKIN should either be disconnected or pulled up.
When the DSI uses sliding window address mode (DCR[SLDWA] = 1), the external HA[11–13] signals must be
connected (tied) to the correct voltage levels so that the host can perform the first access to the DCR. After reset, the
DSI expects full address mode (DCR[SLDWA] = 0). The DCR address in the DSI memory map is 0x1BE000, which
requires the following connections:
— HA11 must be pulled high (1)
— HA12 must be pulled high (1)
— HA13 must be pulled low (0)
The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK.
In single-master mode (BCR[EBM] = 0) with internal arbitration (PPC_ACR[EARB] = 0):
— BG, DBG, and TS can be left unconnected.
— EXT_BG[2–3], EXT_DBG[2–3], and GBL can be left unconnected if they are multiplexed to the system bus
functionality. For any other functionality, connect the signal lines based on the multiplexed functionality.
— BR must be pulled up.
— EXT_BR[2–3] must be pulled up if multiplexed to the system bus functionality.
If there is an external bus master (BCR[EBM] = 1):
— BR, BG, DBG, and must be pulled up.
— EXT_BR[2–3], EXT_BG[2–3], and EXT_DBG[2–3] must be pulled up if multiplexed to the system bus
functionality.
In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other
modes, they must be pulled up.
Figure 34. VCCSYN Bypass
VDD
0.01 F
10 F
VCCSYN
10
Ω
10nH
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MSC8112TVT2400V | 制造商:Freescale Semiconductor 功能描述:Dual Core Digital Signal Processor |
| MSC8113 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Tri-Core Digital Signal Processor |
| MSC8113TMP3600V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8113TMP4800V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，FCBGA 供應商設備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| MSC8113TVT3600V | 功能描述:DSP TRI-CORE 431-FCPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:StarCore 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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