參數(shù)資料
型號： MSC8101M1250C
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： Network Digital Signal Processor
中文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 57/104頁
文件大?。?/td> 877K
代理商： MSC8101M1250C
AC Timings
MSC8101 Technical Data, Rev. 16
Freescale Semiconductor
2-17
Figure 2-8
and
Figure 2-9
show HDI16 read signal timing.
Figure 2-10
and
Figure 2-11
show HDI16 write signal
timing.
48
Host data input minimum hold time after write data strobe deassertion
8
Host data input minimum hold time after HACK write deassertion
Read data strobe minimum assertion to output data active from high
impedance
4
HACK read minimum assertion to output data active from high impedance
Read data strobe maximum assertion to output data valid
4
HACK read maximum assertion to output data valid
Read data strobe maximum deassertion to output data high impedance
4
HACK read maximum deassertion to output data high impedance
Output data minimum hold time after read data strobe deassertion
4
Output data minimum hold time after HACK read deassertion
HCS[1–2] minimum assertion to read data strobe assertion
4
HCS[1–2] minimum assertion to write data strobe assertion
8
—
5.0
ns
49
—
5.0
ns
ns
50
(2.0
×
T
C
) + 5.0
Note 11
51
—
5.0
ns
52
—
—
—
5.0
5.0
5.0
ns
ns
ns
53
54
55
56
57
HCS[1–2] maximum assertion to output data valid
HCS[1–2] minimum hold time after data strobe deassertion
9
HA[0–3], HRW minimum set-up time before data strobe assertion
9
Read
Write
HA[0–3], HRW minimum hold time after data strobe deassertion
9
T
C
+ 5.0
—
—
Note 11
0.0
ns
ns
0
5.0
5.0
ns
ns
ns
58
—
61
Maximum delay from read data strobe deassertion to host request deassertion
for “Last Data Register” read
4, 5, 10
Maximum delay from write data strobe deassertion to host request deassertion
for “Last Data Register” write
5,8,10
Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)
deassertion to HREQ assertion.
Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)
assertion to HREQ deassertion
T
C
= 1/ DSPCLK. At 300 MHz, T
C
= 3.3 ns
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
V
CC
= 3.3 V ± 0.3 V; T
J
=
–40°C to +100 °C, C
L
= 50 pF
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
In 64-bit mode, The “l(fā)ast data register” is the register at address $7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
This timing is applicable only if a read from the “l(fā)ast data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
This timing is applicable only if two consecutive reads from one of these registers are executed.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10.
The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
(treat as level Host Request).
11.
Compute the value using the expression.
(3.5
×
T
C
)
+ 5.0
Note 11
ns
62
(3.0
×
T
C
)
+ 5
Note 11
ns
63
(5.0
×
T
C
) + 5.0
Note 11
ns
64
(3.5
×
T
C
)
+ 5.0
Note 11
ns
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Table 2-19.
Host Interface (HDI16) Timing
1, 2
(Continued)
Number
Characteristics
3
Expression
Value
Unit
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MSC8101M1375C 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Network Digital Signal Processor
MSC8101M1375F 功能描述:DSP 16BIT 275MHZ CPM 332-FCPBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標準包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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MSC8101UG/D 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Network Digital Signal Processor
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