參數(shù)資料
型號(hào)： MSC7116VF1000
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
中文描述： 低成本16位數(shù)字信號(hào)處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC
文件頁(yè)數(shù)： 32/56頁(yè)
文件大?。?/td> 719K
代理商： MSC7116VF1000
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Electrical Characteristics
Freescale Semiconductor
32
2.5.7
HDI16 Signals
Table 25. Host Interface (HDI16) Timing
1, 2
No.
Characteristics
3
Expression
Value
Unit
40
44a
Host Interface Clock period
Read data strobe minimum assertion width
4
HACK read minimum assertion width
Read data strobe minimum deassertion width
4
HACK read minimum deassertion width
Read data strobe minimum deassertion width
4
after “Last Data Register”
reads
5,6
, or between two consecutive CVR, ICR, or ISR reads
7
HACK minimum deassertion width after “Last Data Register” reads
5,6
Write data strobe minimum assertion width
8
HACK write minimum assertion width
Write data strobe minimum deassertion width
8
HACK write minimum deassertion width after ICR, CVR and Data Register
writes
5
Host data input minimum setup time before write data strobe deassertion
8
Host data input minimum setup time before HACK write deassertion
Host data input minimum hold time after write data strobe deassertion
8
Host data input minimum hold time after HACK write deassertion
Read data strobe minimum assertion to output data active from high
impedance
4
HACK read minimum assertion to output data active from high impedance
Read data strobe maximum assertion to output data valid
4
HACK read maximum assertion to output data valid
Read data strobe maximum deassertion to output data high impedance
4
HACK read maximum deassertion to output data high impedance
Output data minimum hold time after read data strobe deassertion
4
Output data minimum hold time after HACK read deassertion
HCS[1–2] minimum assertion to read data strobe assertion
4
HCS[1–2] minimum assertion to write data strobe assertion
8
HCS[1–2] maximum assertion to output data valid
HCS[1–2] minimum hold time after data strobe deassertion
9
HA[0–2], HRW minimum setup time before data strobe assertion
9
HA[0–2], HRW minimum hold time after data strobe deassertion
9
Maximum delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read
4, 5, 10
Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write
5,8,10
Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
1.
T
CORE
= core clock period. At 300 MHz, T
CORE
= 3.333 ns.
2.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3.
V
DD
= 3.3 V ± 0.15 V; T
J
=
–40°C to +105 °C, C
L
= 30 pF for maximum delay timings and C
L
= 0 pF for minimum delay timings.
4.
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5.
For 64-bit transfers, the “l(fā)ast data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6.
This timing is applicable only if a read from the “l(fā)ast data register” is followed by a read from the RX[0–3] registers without first
polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7.
This timing is applicable only if two consecutive reads from one of these registers are executed.
8.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10.
The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
11.
Compute the value using the expression.
12.
The read and write data strobe minimum deassertion width for non-”last data register” accesses in single and dual data strobe
modes is based on timings 57 and 58.
T
CORE
Note 1
Note 11
ns
ns
2.0
×
T
CORE
+ 9.0
44b
1.5
×
T
CORE
Note 11
ns
44c
2.5
×
T
CORE
Note 11
ns
45
1.5
×
T
CORE
Note 11
ns
46
2.5
×
T
CORE
Note 11
ns
47
—
2.5
ns
48
—
2.5
ns
49
—
1.0
ns
50
(2.0
×
T
CORE
) + 8.0
Note 11
ns
51
—
9.0
ns
52
—
—
—
1.0
0.5
0.0
ns
ns
ns
ns
ns
ns
ns
ns
53
54
55
56
57
58
61
(2.0
×
T
CORE
) + 6.0
—
—
—
(3.0
×
T
CORE
)
+ 6.0
Note 11
0.5
5.0
5.0
Note 11
62
(3.0
×
T
CORE
)
+ 6.0
Note 11
ns
63
(2.0
×
T
CORE
) + 1.0
Note 11
ns
64
(5.0
×
T
CORE
)
+ 6.0
Note 11
ns
Notes:
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MSC7116VM1000 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 7116 STARLITE - PBF RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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