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參數(shù)資料
| 型號： | MR80C154-25/883D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 42/214頁 |
| 文件大?。?/td> | 61013K |
| 代理商： | MR80C154-25/883D |
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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is transferred to a temporary
register, and latched after two positive edges on TOSC1. The user should not write a new value before the
contents of the temporary register have been transferred to its destination. Each of the three mentioned registers
have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2A write
in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status
Register – ASSR has been implemented
When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2A, or TCCR2A,
the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device.
Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the
Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during
writing to OCR2A or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the
OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake
up
If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode, precautions
must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be
reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will
not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-
save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1
cycle has elapsed:
a.
Write a value to TCCR2A, TCNT2, or OCR2A.
b.
Wait until the corresponding Update Busy Flag in ASSR returns to zero.
c.
Enter Power-save or ADC Noise Reduction mode.
When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running,
except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby
mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The
user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from
Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a
wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the
Oscillator is in use or a clock signal is applied to the TOSC1 pin
Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the
timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value.
After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from
the instruction following SLEEP
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since
TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register
synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When
waking up from Power-save mode, and the I/O clock (clk
I/O) again becomes active, TCNT2 will read as the
previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after
waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The
recommended procedure for reading TCNT2 is thus as follows:
a.
Write any value to either of the registers OCR2A or TCCR2A.
b.
Wait for the corresponding Update Busy Flag to be cleared.
c.
Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes
3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can
read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer
clock and is not synchronized to the processor clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ83C154XXX-30P883D | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQFP44 |
| MD83C154CXXX-L16/883D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C154-16/883 | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| MR83C154CXXX-25P883 | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44 |
| MQ83C154CXXX-36/883D | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C154-30 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR80C154-36 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR80C154-L16 | 制造商:TEMIC 制造商全稱:TEMIC Semiconductors 功能描述:CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller |
| MR80C31BH | 制造商:ROCHESTER 制造商全稱:ROCHESTER 功能描述:CMOS SINGLE - CHIP 8-BIT MICROCOMPUTER 64K program Memory Space |
| MR80C31BH/B | 制造商:n/a 功能描述:8506401XA |
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