參數(shù)資料
型號: MQ80C154-16P883
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù): 82/142頁
文件大?。?/td> 61013K
代理商: MQ80C154-16P883
172
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
20.11 Register description
20.11.1
UDRn – USART I/O Data Register
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address
referred to as USART Data Register or UDRn. The Transmit Data Buffer Register (TXB) will be the destination for
data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the
Receive Data Buffer Register (RXB).
For 5-, 6- or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the
Receiver.
The transmit buffer can only be written when the UDREn Flag in the UCSRnA Register is set. Data written to UDRn
when the UDREn Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit
buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the
Shift Register is empty. Then the data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is
accessed. Due to this behavior of the receive buffer, do not use Read-Modify-Write instructions (SBI and CBI) on
this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of
the FIFO.
20.11.2
UCSRnA – USART Control and Status Register A
Bit 7 – RXCn: USART Receive Complete n
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
(i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and conse-
quently the RXCn bit will become zero. The RXCn Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIEn bit).
Bit 6 – TXCn: USART Transmit Complete n
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new
data currently present in the transmit buffer (UDRn). The TXC Flag bit is automatically cleared when a transmit
complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC Flag can generate
a Transmit Complete interrupt (see description of the TXCIE bit).
Bit 5 – UDREn: USART Data Register Empty n
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is
empty, and therefore ready to be written. The UDREn Flag can generate a Data Register Empty interrupt (see
description of the UDRIEn bit).
UDREn is set after a reset to indicate that the Transmitter is ready.
Bit
7
6543
210
(0xC6)
RXB[7:0]
UDRn (Read)
TXB[7:0]
UDRn (Write)
Read/Write
R/W
Initial Value
0
0000
000
Bit
765
432
10
(0xC0)
RXCn
TXCn
UDREn
FEn
DORn
UPEn
U2Xn
MPCMn
UCSRnA
Read/Write
R
R/W
RRR
R
R/W
Initial Value
001
000
00
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