參數(shù)資料
型號(hào): mPD789326GB-xxx-8ET
廠商: NEC Corp.
元件分類: 8位微控制器
英文描述: 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash
中文描述: 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存
文件頁數(shù): 45/96頁
文件大?。?/td> 482K
代理商: MPD789326GB-XXX-8ET
Preliminary Product Information U14673EJ1V0PM00
45
μ
PD789322,789324,789326,789327
5.5.3 Watchdog timer control register
The watchdog timer is controlled by the following register.
Watchdog timer mode register (WDTM)
(1) Watchdog timer mode register (WDTM)
This register is used to set the watchdog timer operation mode and whether to enable or disable counting.
WDTM is set using a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Figure 5-21. Format of Watchdog Timer Mode Register
Symbol
<7>
6
5
4
3
2
1
0
Address
After reset
R/W
WDTM
RUN
0
0
WDTM4
WDTM3
0
0
0
FFF9H
00H
R/W
RUN
Watchdog timer operation selection
Note 1
0
Counting stopped
1
Counter cleared and counting starts
WDTM4
WDTM3
Watchdog timer operation mode selection
Note 2
0
0
Operation stopped
0
1
Interval timer mode (when an overflow occurs, a maskable interrupt is generated)
Note 3
1
0
Watchdog timer mode 1 (when an overflow occurs, a non-maskable interrupt is generated)
1
1
Watchdog timer mode 2 (when an overflow occurs, a reset operation is activated)
Notes 1.
Once the RUN bit has been set (1), it is impossible to clear it (0) by software. Consequently, once
counting begins, it cannot be stopped by any means other than RESET input.
2.
Once WDTM3 and WDTM4 have been set (1), it is impossible to clear them (0) by software.
3.
The interval timer starts operating as soon as the RUN bit is set to 1.
Cautions 1. When the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time
will be up to 0.8% shorter than the time specified by the watchdog timer clock selection
register.
2. To use watchdog timer mode 1 or 2, be sure to set WDTM4 to 1 after confirming that
WDTIF (bit 0 of interrupt request flag 0 (IF0)) has been set to 0. If WDTIF is 1, selecting
watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant
rewriting ends.
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