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參數(shù)資料
| 型號(hào)： | mPD705101GM-100-8ED |
| 廠商： | NEC Corp. |
| 英文描述： | V831TM 32-BIT MICROPROCESSOR |
| 中文描述： | V831TM 32位微處理器 |
| 文件頁(yè)數(shù)： | 28/72頁(yè) |
| 文件大?。?/td> | 302K |
| 代理商： | MPD705101GM-100-8ED |
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μ
PD705101
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13. STANDBY FUNCTION
The following two standby modes can be used.
(1) HALT mode
In this mode, the clock generator (oscillation circuit and PLL synthesizer) operates, but the operating clock of the
CPU is stopped. The other internal peripheral functions are supplied with the clock and continue operation. By
using this mode in combination with the normal mode, the power consumption of the entire system can be reduced.
(2) STOP mode
In this mode, the clock generator (PLL synthesizer) is stopped and the entire system is stopped. Because the
PLL synthesizer and internal peripheral functions are stopped, the power consumption can be reduced more than
in the HALT mode.
Because the clock output of the PLL synthesizer is stopped, make sure that sufficient time elapses after the STOP
mode is released until the oscillation circuit, CPU clock, and bus clock are stabilized. The PLL circuit may require
lock up time depending on the program.
Table 13-1 shows the operations of the clock generator in the HALT and STOP modes. By selecting each mode
as the application requires, the power consumption of the system can be efficiently reduced.
Table 13-1. Operation of Clock Generator in Standby Mode
Standby Mode
Oscillation Circuit
(OSC)
PLL Synthesizer
Clock Supply to
Peripheral I/O
Clock Supply to
CPU
Normal mode
HALT mode
×
STOP mode
×
×
×
Remark
: Operates
×
: Stopped
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