- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382345 > MPC99J93 (Motorola, Inc.) Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC99J93 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver |
| 中文描述： | 智能動(dòng)態(tài)時(shí)鐘開關(guān)（IDC機(jī)房）PLL時(shí)鐘驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 265K |
| 代理商： | MPC99J93 |
MPC99J93
MOTOROLA TIMING SOLUTIONS
2
Figure 2. 32--Lead Pinout
(Top View)
GND
V
Q
Q
Q
Q
Q
Q
V
M
A
C
C
S
C
C
G
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
MPC99J93
Ext_FB
Ext_FB
GND
Clk_Selected
Inp1bad
Inp0bad
VCC
PLL_En
Man_Override
VCC_PLL
VCC
Qa0
Qa0
Qa1
Qa1
Table 1. Pin Descriptions
Pin Name
I/O
Pin Definition
CLK0, CLK0
CLK1, CLK1
LVPECL Input
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
LVPECL Input
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Qa0:1, Qa0:1
LVPECL Output
Differential 1x output pairs. Connect one QAx pair to Ext_FB.
Qb0:2, Qb0:2
LVPECL Output
Differential 2x output pairs
Inp0bad
LVCMOS Output
Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Inp1bad
LVCMOS Output
Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Clk_Selected
LVCMOS Output
‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected
Alarm_Reset
LVCMOS Input
‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one--shotted”
(50k
pullup)
Sel_Clk
LVCMOS Input
‘0’ selects CLK0, ‘1’ selects CLK1 (50k
pulldown)
Manual_Override
LVCMOS Input
‘1’ disables internal clock switch circuitry (50k
pulldown)
PLL_En
LVCMOS Input
‘0’ bypasses selected input reference around the phase--locked loop (50k
pullup)
MR
LVCMOS Input
‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k
pullup)
VCCA
Power Supply
PLL power supply
VCC
Power Supply
Digital power supply
GNDA
Power Supply
PLL ground
GND
Power Supply
Digital ground
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPD-425V | 250W DC-DC POWER SUPPLY INPUT RANGE: 40~57VDC |
| MPE-902M | SWITCHING POWER SUPPLY |
| MPF102G | JFET VHF Amplifier |
| MPF4392G | JFET Switching Transistors N−Channel − Depletion |
| MPF4393G | JFET Switching Transistors N−Channel − Depletion |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC99J93AC | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC99J93ACR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC99J93FA | 功能描述:IC CLOCK DRIVER LV 1:5 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MPCA06 | 制造商:Motorola Inc 功能描述: |
| MPCB-20.0-0-E563 | 制造商:TE Connectivity 功能描述:MPCB-20.0-0-E563 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。