參數(shù)資料
型號(hào)： MPC97H74AER2
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 10/13頁(yè)
文件大小： 0K
描述： IC PLL CLK GEN 1:14 3.3V 52-LQFP
標(biāo)準(zhǔn)包裝： 1,500
類型： PLL 時(shí)鐘發(fā)生器
PLL： 帶旁路
輸入： LVCMOS
輸出： LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 2:14
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 125MHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-TQFP（10x10）
包裝： 帶卷 (TR)
MPC97H74 REVISION 5 JANUARY 9, 2013
6
2013 Integrated Device Technology, Inc.
MPC97H74 Data Sheet
3.3 V 1:14 LVCMOS PLL CLOCK GENERATOR
APPLICATIONS INFORMATION
MPC97H74 Configurations
Configuring the MPC97H74 amounts to properly
configuring the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
where fREF is the reference frequency of the selected input
clock source (CCLKO or CCLK1), M is the PLL feedback
divider and N is a output divider. M is configured by the
FSEL_FB[0:1] and N is individually configured for each
output bank by the FSEL_A, FSEL_B and FSEL_C inputs.
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 500 MHz (210 to 450 MHz for
industrial temperature range) in order to achieve stable PLL
operation:
fVCO,MIN (fREF VCO_SEL M) fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-two
or a divide-by-four and can be used to situate the VCO into
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio. The output frequency for each
bank can be derived from the VCO frequency and the output
divider:
fQA[4:0] = fVCO (VCO_SEL NA)
fQB[4:0] = fVCO (VCO_SEL NB)
fQC[3:0] = fVCO (VCO_SEL NC)
Table 10 shows the various PLL feedback and output
dividers. The output dividers for the three output banks allow
the user to configure the outputs into 1:1, 2:1, 3:2, and 3:2:1
frequency ratios. Figure 3 and Figure 4 display example
configurations for the MPC97H74:
fOUT = fREF M N
fREF
PLL
VCO_SEL
N
fOUT
M
Table 10. MPC97H74 Dividers
Divider
Function
VCO_SEL
Values
M
PLL feedback
FSEL_FB[0:1]
2
8, 12, 16, 24
4
16, 24, 32, 48
NA
Bank A Output Divider
FSEL_A
2
4, 8
4
8, 16
NB
Bank B Output Divider
FSEL_B
2
4, 8
4
8, 16
NC
Bank C Output Divider
FSEL_C
2
8, 12
4
16, 24
Figure 3. Example Configuration
Figure 4. Example Configuration
MPC97H74
fREF = 20.83 MHz
125 MHz
62.5 MHz
20.83 MHz (Feedback)
62.5 MHz
CCLK0
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
CCLK1
CCLK_SEL
FB_IN
0
1
0
11
0
Frequency Range
Min
Max
Input
8.33 MHz
20.83 MHz
QA outputs
50 MHz
125 MHz
QB outputs
25 MHz
62.5 MHz
QC outputs
25 MHz
62.5 MHz
MPC97H74
fREF = 25 MHz
100 MHz
50 MHz
25 MHz (Feedback)
33.3 MHz
CCLK0
VCO_SEL
FSEL_A
FSEL_B
FSEL_C
FSEL_FB[1:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
CCLK1
CCLK_SEL
FB_IN
0
1
01
0
MPC97H74 example configuration (feedback of
QFB = 25 MHz, VCO_SEL =
2, M = 8, NA = 2,
NB = 4, NC = 6, fVCO = 400 MHz).
Frequency
Range
TA = 0°C to +70°C TA = -40°C to +85°C
Input
12.50 - 31.25 MHz 13.125 - 28.125 MHz
QA outputs
50.00 - 125.0 MHz
52.50 - 112.5 MHz
QB outputs
25.00 - 62.50 MHz
26.25 - 56.25 MHz
QC outputs
16.67 - 41.67 MHz
17.50 - 37.50 MHz
MPC97H74 example configuration (feedback of
QFB = 20.83 MHz, VCO_SEL =
2, M = 12, NA = 2,
NB = 4, NC = 4, fVCO = 500 MHz). TA = 0°C to 70°C
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