- 您現在的位置：買賣IC網 > PDF目錄9017 > MPC97H74AER2 (IDT, Integrated Device Technology Inc)IC PLL CLK GEN 1:14 3.3V 52-LQFP PDF資料下載
參數資料
| 型號： | MPC97H74AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 1/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK GEN 1:14 3.3V 52-LQFP |
| 標準包裝： | 1,500 |
| 類型： | PLL 時鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:14 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 125MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設備封裝： | 52-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
DATASHEET
3.3 V 1:14 LVCMOS PLL Clock Generator
MPC97H74
NRND
MPC97H74 REVISION 5 JANUARY 9, 2013
1
2013 Integrated Device Technology, Inc.
The MPC97H74 is a 3.3 V compatible, 1:14 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With output
frequencies up to 125 MHz and output skews less than 175 ps the device meets
the needs of the most demanding clock applications.
Features
1:14 PLL based low-voltage clock generator
3.3 V power supply
Internal power-on reset
Generates clock signals up to 125 MHz
Maximum output skew of 175 ps
Two LVCMOS PLL reference clock inputs
External PLL feedback supports zero-delay capability
Various feedback and output dividers (see application section)
Supports up to three individual generated output clock frequencies
Drives up to 28 clock lines
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MPC974
52-lead Pb-free Package
NRND – Not Recommend for New Designs
Use replacement part ICS87974CYILF
The MPC97H74 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC97H74 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.
The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range.
The MPC97H74 features frequency programmability between the three output bank outputs as well as the output to input
relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, and 3:2:1 can be realized. Additionally, the device supports a separate
configurable feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_SEL
pin provides an extended PLL input reference frequency range.
The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two
alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL
bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output
dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL
characteristics do not apply.
The MPC97H74 has an internal power-on reset.
The MPC97H74 is fully 3.3 V compatible and requires no external loop filter components. All inputs (except XTAL) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an
effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.
AE SUFFIX
52-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 848D-03
MPC97H74
3.3 V 1:14 LVCMOS
PLL CLOCK GENERATOR
NRND – Not Recommend for New Designs
相關PDF資料 |
PDF描述 |
|---|---|
| VE-202-MY-F3 | CONVERTER MOD DC/DC 15V 50W |
| VI-J7J-MZ-F4 | CONVERTER MOD DC/DC 36V 25W |
| VE-202-MY-F2 | CONVERTER MOD DC/DC 15V 50W |
| VI-B32-MV-F4 | CONVERTER MOD DC/DC 15V 150W |
| MPC9772FAR2 | IC PLL CLK GEN 1:12 3.3V 52-LQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC97H74FA | 功能描述:IC PLL CLK GENERATOR 1:14 52LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| MPC980 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DUAL 3.3V PLL CLOCK GENERATOR |
| MPC9817 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers |
| MPC9817EN | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9817ENR2 | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復。