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參數(shù)資料
| 型號： | MPC9259FA |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| 封裝： | LQFP-32 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 493K |
| 代理商： | MPC9259FA |
MPC9259
MOTOROLA
TIMING SOLUTIONS
8
Table 10. Test and Debug Configuration for TEST
T[2:0]
TEST output
T2
T1
T0
0
12-bit shift register outa
0
1
Logic 1
0
1
0
fXTAL ÷ 2
0
1
M-Counter out
1
0
FOUT
1
0
1
Logic 0
1
0
M-Counter out in PLL-bypass mode
1
FOUT
÷ 4
a.
Clocked out at the rate of S_CLOCK
Table 11. Debug Configuration for PLL bypassa
Output
Configuration
FOUT
S_CLOCK
÷ N
TEST
M-Counter outb
a.
T[2:0] = 110. AC specifications do not apply in PLL bypass
mode
b.
Clocked out at the rate of S_CLOCK
÷ (2N)
Figure 3. Serial Interface Timing Diagram
S_CLOCK
S_DATA
S_LOAD
M[6:0]
N[1:0]
P_LOAD
T2
T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
M, N
First
Bit
Last
Bit
Power Supply Filtering
The MPC9259 is a mixed analog/digital product and as such
it exhibits some sensitivities that would not necessarily be
seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen on
the power supply pins. The MPC9259 provides separate
power supplies for the digital circuitry (VCC) and the internal
PLL (VCC_PLL) of the device. The purpose of this design
technique is to try and isolate the high switching noise digital
outputs
from
the
relatively
sensitive
internal
analog
phase–locked loop. In a controlled environment such as an
evaluation board, this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCC_PLL pin for the MPC9259.
Figure 4 illustrates a typical power supply filter scheme. The
MPC9259 is most susceptible to noise with spectral content in
the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that will
be seen between the VCC supply and the MPC9259 pin of the
MPC9259. From the data sheet, the VCC_PLL current (the
current sourced through the VCC_PLL pin) is typically TBD
mA (TBD maximum), assuming that a minimum of 3.135V
must be maintained on the VCC_PLL pin, very little DC voltage
drop can be tolerated when a 3.3V VCC supply is used. The
resistor shown in Figure 4 must have a resistance of TBD
to
meet the voltage drop criteria. The RC filter pictured will
provide
a
broadband
filter
with
approximately
100:1
attenuation for noise whose spectral content is above 20 kHz.
As the noise frequency crosses the series resonant point of an
individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Generally, the resistor/capacitor
filter will be cheaper, easier to implement and provide an
adequate level of supply filtering. A higher level of attenuation
can be achieved by replacing the resistor with an appropriate
valued inductor. A 1000
H choke will show a significant
impedance at 10 kHz frequencies and above. Because of the
current draw and the voltage that must be maintained on the
VCC_PLL pin, a low DC resistance inductor is required (less
than TBD
).
Figure 4. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC9259
C3
C1 = 33...100 nF
R1
VCC
C3 = TBD F
C2 = 10 nF
R1 = TBD
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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..
.
MPC9259
900 MHz Low Voltage LVDS Clock Symthesizer
NETCOM
IDT 900 MHz Low Voltage LVDS Clock Symthesizer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC9259
8
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