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參數(shù)資料
| 型號： | MPC92433AER2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER LVPECL 48-LQFP |
| 標準包裝： | 2,000 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 1.428GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC92433 Data Sheet
1428MHZ DUAL OUTPUT LVPECL CLOCK SYNTHESIZER
MPC92433 REVISION 3 FEBRUARY 6, 2013
4
2013 Integrated Device Technology, Inc.
Table 2. Function Table
Control
Default(1)
1. Default states are set by internal input pull-up or pull-down resistors of 75 k
01
Inputs
REF_SEL
1
Selects REF_CLK input as PLL reference clock
Selects the XTAL interface as PLL reference
clock
M[9:0]
01 1111 0100b(2)
2. If fREF = 16 MHz, the default configuration will result in an output frequency of 250 MHz.
PLL feedback divider (10-bit) parallel programming interface
NA[2:0]
010
PLL post-divider parallel programming interface. See Table 9
NB
0
PLL post-divider parallel programming interface. See Table 9
P
1
PLL pre-divider parallel programming interface. See Table 8
PLOAD
0
Selects the parallel programming interface. The
internal PLL divider settings (M, NA, NB and P) are
equal to the setting of the hardware pins. Leaving the
M, NA, NB and P pins open (floating) results in a
default PLL configuration with fOUT = 250 MHz. See
application/programming section.
Selects the serial (I2C) programming interface.
The internal PLL divider settings (M, NA, NB and
P) are set and read through the serial interface.
ADR[1:0]
00
Address bit = 0
Address bit = 1
SDA, SCL
See Programming the MPC92433
BYPASS
1
PLL function bypassed
fQA=fREF÷ NA and
fQB=fREF÷ (NA NB)
PLL function enabled
fQA = (fREF÷ P) M ÷ NA and
fQB = (fREF ÷ P) M ÷ (NA NB)
TEST_EN
0
Application mode. Test mode disabled.
Factory test mode is enabled
CLK_STOPx
1
Output Qx is disabled in logic low state. Synchronous
disable is only guaranteed if NB = 0.
Output Qx is synchronously enabled
MR
The device is reset. The output frequency is zero and
the outputs are asynchronously forced to logic low
state.
After releasing reset (upon the rising edge of MR and
independent on the state of PLOAD), the MPC92433
reads the parallel interface (M, NA, NB and P) to
acquire a valid startup frequency configuration. See
application/programming section.
The PLL attempts to lock to the reference signal.
The tLOCK specification applies.
Outputs
LOCK
PLL is not locked
PLL is frequency locked
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應商設備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC92439EI | 功能描述:時鐘合成器/抖動清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439EIR2 | 功能描述:時鐘合成器/抖動清除器 FSL 900MHz LVPECL Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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