參數(shù)資料
型號: MPC8572LVTATLE
廠商: Freescale Semiconductor
文件頁數(shù): 38/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
132
Freescale Semiconductor
System Design Information
21.10 Guidelines for High-Speed Interface Termination
21.10.1 SerDes 1 Interface Entirely Unused
If the high-speed SerDes 1 interface is not used at all, the unused pin should be terminated as described in
this section.
The following pins must be left unconnected (float):
SD1_TX[7:0]
SD1_TX[7:0]
Reserved pins C24, C25, H26, H27
The following pins must be connected to XGND_SRDS1:
SD1_RX[7:0]
SD1_RX[7:0]
SD1_REF_CLK
SD1_REF_CLK
Pins K32 and C29 must be tied to XVDD_SRDS1. Pins K31 and C30 must be tied to XGND_SRDS1
through a 300-
Ω resistor.
The POR configuration pin cfg_srds1_en on TSEC2_TXD[5] can be used to power down SerDes 1 block
for power saving. Note that both SVDD_SRDS1 and XVDD_SRDS1 must remain powered.
21.10.2 SerDes 1 Interface Partly Unused
If only part of the high speed SerDes 1 interface pins are used, the remaining high-speed serial I/O pins
should be terminated as described in this section.
The following pins must be left unconnected (float) if not used:
SD1_TX[7:0]
SD1_TX[7:0]
Reserved pins: C24, C25, H26, H27
The following pins must be connected to XGND_SRDS1 if not used:
SD1_RX[7:0]
SD1_RX[7:0]
Pins K32 and C29 must be tied to XVDD_SRDS1. Pins K31 and C30 must be tied to XGND_SRDS1
through a 300-
Ω resistor.
21.10.3 SerDes 2 Interface (SGMII) Entirely Unused
If the high-speed SerDes 2 interface (SGMII) is not used at all, the unused pin should be terminated as
described in this section.
The following pins must be left unconnected (float):
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