參數(shù)資料
型號(hào): MPC8378E-MDS-PB
廠商: Freescale Semiconductor
文件頁數(shù): 82/128頁
文件大?。?/td> 0K
描述: BOARD PROCESSOR FOR MDS S
標(biāo)準(zhǔn)包裝: 1
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8378
所含物品:
MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
57
clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample
the data, and therefore used in the equations.
11.3.2.1
High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
tCLK_DELAY + tDATA_DELAY + tODLY + tSHSIVKH < 1.5 × tSHSCK
Eqn. 15
tCLK_DELAY + tDATA_DELAY < 1.5 × tSHSCK tODLY tSHSIVKH
Eqn. 16
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
tCLK_DELAY + tDATA_DELAY < 30 14 5
tCLK_DELAY + tDATA_DELAY < 11
11.3.2.2
High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
0.5
× tSHSCK < tCLK_DELAY + tDATA_DELAY + tOH tSHSIXKH + tINT_CLK_DLY
Eqn. 17
0.5
× tSHSCK tOH + tSHSIXKH tINT_CLK_DLY < tCLK_DELAY + tDATA_DELAY
Eqn. 18
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10 2.5 + (–1.5) < tCLK_DELAY + tDATA_DELAY
6 < tCLK_DELAY + tDATA_DELAY
11.3.2.3
High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
0.5
× tSHSCK tOH + tSHSIXKH < tCLK_DELAY + tDATA_DELAY < 1.5 × tSHSCK tODLY tSHSIVKH
Eqn. 19
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the chip.
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