參數(shù)資料
型號： MPC8323ECZQAFDC
廠商： Freescale Semiconductor
文件頁數(shù)： 7/82頁
文件大?。?/td> 0K
描述： IC MPU PWRQUICC II 516-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8323E PowerQUICC II Pro Processor
標(biāo)準(zhǔn)包裝： 40
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 333MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
配用： MPC8323E-RDB-ND - BOARD REFERENCE DESIGN
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
Freescale Semiconductor
15
DDR1 and DDR2 SDRAM
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR1 and DDR2 SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
Table 16 provides the input AC timing specifications for the DDR2 SDRAM (Dn_GVDD(typ) = 1.8 V).
Table 17 provides the input AC timing specifications for the DDR1 SDRAM (Dn_GVDD(typ) = 2.5 V).
Table 18 provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions with D
n_GVDD of 1.8 ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF
nREF – 0.25
V
—
AC input high voltage
VIH
MVREF
nREF + 0.25
—
V
—
Table 17. DDR1 SDRAM Input AC Timing Specifications for 2.5 V Interface
At recommended operating conditions with D
n_GVDD of 2.5 ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—
MVREF
nREF – 0.31
V
—
AC input high voltage
VIH
MVREF
nREF + 0.31
—
V
—
Table 18. DDR1 and DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with D
n_GVDD of (1.8 or 2.5 V) ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MDM
tCISKEW
ps
1, 2
266 MHz
200 MHz
–750
–1250
750
1250
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ±(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
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參數(shù)描述
MPC8323ECZQAFDCA 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
MPC8323EEC 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:PowerQUICC? II Pro Integrated Communications Processor Family Hardware Specifications
MPC8323E-MDS-PB 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8323E PROCESSOR BOARD RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8323E-RDB 功能描述:開發(fā)板和工具包 - 其他處理器 REFERENCE DESIGN PQII PR RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
MPC8323E-RDB 制造商:Freescale Semiconductor 功能描述:MPC8323E Integrated Multiservice Gateway
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