參數(shù)資料
型號： MPC8321ZQAFDCA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 333 MHz, RISC PROCESSOR, PBGA516
封裝： 27 X 27 MM, 2.25 MM HEIGHT, 1 MM PITCH, PLASTIC, PBGA-516
文件頁數(shù)： 43/82頁
文件大小： 1059K
代理商： MPC8321ZQAFDCA
MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
48
Freescale Semiconductor
USB
20 USB
This section provides the AC and DC electrical specifications for the USB interface of the MPC8323E.
20.1
USB DC Electrical Characteristics
Table 53 provides the DC electrical characteristics for the USB interface.
20.2
USB AC Electrical Specifications
Table 54 describes the general timing parameters of the USB interface of the MPC8323E.
Figure 41 provide the AC test load for the USB.
Figure 41. USB AC Test Load
Table 53. USB DC Electrical Characteristics1
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2OVDD + 0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
High-level output voltage, IOH = –100 μAVOH
OVDD – 0.2
—
V
Low-level output voltage, IOL = 100 μAVOL
—0.2
V
Input current
IIN
—±5
μA
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 54. USB General Timing Parameters
Parameter
Symbol1
Min
Max
Unit
Notes
USB clock cycle time
tUSCK
20.83
—
ns
Full speed 48 MHz
USB clock cycle time
tUSCK
166.67
—
ns
Low speed 6 MHz
Skew between TXP and TXN
tUSTSPN
—5
ns
—
Skew among RXP, RXN, and RXD
tUSRSPND
—
10
ns
Full speed transitions
Skew among RXP, RXN, and RXD
tUSRPND
—
100
ns
Low speed transitions
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(state)(signal) for receive signals
and t(first two letters of functional block)(state)(signal) for transmit signals. For example, tUSRSPND symbolizes USB timing (US) for the
USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, tUSTSPN symbolizes USB timing (US) for the USB
transmit signals skew (TS) between TXP and TXN (PN).
2. Skew measurements are done at OVDD/2 of the rising or falling edge of the signals.
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
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