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參數(shù)資料
| 型號： | MPC8241TZQ200D |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 38/58頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 200MHZ 357-PBGA |
| 標準包裝： | 44 |
| 系列： | MPC82xx |
| 處理器類型： | 32-位 MPC82xx PowerQUICC II |
| 速度： | 200MHz |
| 電壓： | 1.8V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應商設備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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MPC8241 Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
43
System Design Information
Place the circuits as closely as possible to the respective input signal pins to minimize noise coupled from
nearby circuits. Routing from the capacitors to the input signal pins should be as direct as possible with
minimal inductance of vias.
Figure 26. PLL Power Supply Filter Circuit
7.2
Decoupling Recommendations
Dynamic power management, large address and data buses, and high operating frequencies enable the
MPC8241 to generate transient power surges and high frequency noise in its power supply, especially
while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC8241 system, and the MPC8241 itself requires a clean, tightly regulated source of power. Therefore,
place at least one decoupling capacitor at each VDD, GVDD_OVDD, and LVDD pin. These decoupling
capacitors receive their power from dedicated power planes in the PCB, using short traces to minimize
inductance. These capacitors should have a value of 0.1 F. To minimize lead inductance, use only ceramic
SMT (surface mount technology) capacitors, preferably 0508 or 0603, on which connections are made
along the length of the part.
In addition, distribute several bulk storage capacitors around the PCB to feed the VDD, GVDD_OVDD, and
LVDD planes and enable quick recharging of the smaller chip capacitors. These bulk capacitors should
have a low ESR (equivalent series resistance) rating to ensure the necessary quick response time, and
should be connected to the power and ground planes through two vias to minimize inductance. Freescale
recommends using bulk capacitors: 100–330 F (AVX TPS tantalum or Sanyo OSCON).
7.3
Connection Recommendations
To ensure reliable operation, connect unused inputs to an appropriate signal level. Tie unused active-low
inputs to OVDD. Connect unused active-high inputs to GND. All no connect (NC) signals must remain
unconnected.
Power and ground connections must be made to all external VDD, GVDD_OVDD, LVDD, and GND pins.
The PCI_SYNC_OUT signal is to be routed halfway out to the PCI devices and then returned to the
PCI_SYNC_IN input.
The SDRAM_SYNC_OUT signal is to be routed halfway out to the SDRAM devices and then returned to
the SDRAM_SYNC_IN input of the MPC8241. The trace length can be used to skew or adjust the timing
window as needed. See the Tundra Tsi107 Design Guide (AN1849) and Freescale application notes
AN2164/D, MPC8245/MPC8241 Memory Clock Design Guidelines: Part 1 and AN2746,
MPC8245/MPC8241 Memory Clock Design Guidelines: Part 2 for more details. Note the
SDRAM_SYNC_IN to PCI_SYNC_IN time requirement (see Table 10).
VDD
AVDD or AVDD2
2.2 F
GND
Low ESL Surface Mount Capacitors
10
Ω
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