參數(shù)資料
型號(hào)： MPC8241TZQ200D
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 37/58頁(yè)
文件大?。?/td> 0K
描述： IC MPU 32BIT 200MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 200MHz
電壓： 1.8V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
42
Freescale Semiconductor
System Design Information
7
System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8241.
7.1
PLL Power Supply Filtering
The AVDD and AVDD2 power signals on the MPC8241 provide power to the peripheral logic/memory bus
PLL and the MPC603e processor PLL. To ensure stability of the internal clocks, the power supplied to the
AVDD and AVDD2 input signals should be filtered of any noise in the 500 kHz to 10 MHz resonant
frequency range of the PLLs. Two separate circuits similar to the one shown in Figure 26 using surface
mount capacitors with minimum effective series inductance (ESL) is recommended for AVDD and AVDD2
power signal pins. In High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), Dr.
Howard Johnson recommends using multiple small capacitors of equal value instead of multiple values.
1F
111118
Not usable
Off
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Note the impact of the relevant revisions for modes 7 and 1E.
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (352 MHz).
5. Limited by maximum CPU operating frequency.
6. Limited by minimum CPU VCO frequency (300 MHz).
7. Limited by maximum CPU VCO frequency (704 MHz).
8. In clock off mode, no clocking occurs inside the MPC8241, regardless of the PCI_SYNC_IN input.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
10.PLL_CFG[0:4] settings that are not listed are reserved.
11.Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
12.In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is
disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for hardware modeling. The
AC timing specifications in this document do not apply in PLL bypass mode.
13.In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic
PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input
signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation and the processor PLL is disabled. The
PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is intended for hardware modeling.
The AC timing specifications in this document do not apply in dual PLL bypass mode.
14.Limited by minimum CPU operating frequency (100 MHz).
15.Limited by minimum memory bus frequency (50 MHz).
Table 18. PLL Configurations (266-MHz Parts) (continued)
Ref 2
PLL_
CFG[0:4] 10,11
266-MHz Part 9
Multipliers
PCI Clock Input
(PCI_SYNC_IN)
Range 1
(MHz)
Periph Logic/
Mem Bus
Clock Range
(MHz)
CPU Clock
Range
(MHz)
PCI-to-Mem
(Mem VCO)
Mem-to-CPU
(CPU VCO)
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