參數(shù)資料
型號: MPC8241LVR266D
廠商: Freescale Semiconductor
文件頁數(shù): 6/58頁
文件大?。?/td> 0K
描述: IC MPU 32BIT 266MHZ PPC 357-PBGA
標準包裝: 44
系列: MPC82xx
處理器類型: 32-位 MPC82xx PowerQUICC II
速度: 266MHz
電壓: 1.8V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應商設備封裝: 357-PBGA(25x25)
包裝: 托盤
MPC8241 Integrated Processor Hardware Specifications, Rev. 10
14
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 7 provides the operating frequency information for the MPC8241 at recommended operating
conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V.
4.5.1
Clock AC Specifications
Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in
Section 4.5.2, “Input AC Timing Specifications.These specifications are for the default driver strengths
indicated in Table 4. Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled
number items listed in Table 8.
Table 7. Operating Frequency
Characteristic
166 MHz
200 MHz
266 MHz
Unit
VDD/AVDD/AVDD2 = 1.8 ± 100 mV
Min
Max
Min
Max
Min
Max
Processor frequency (CPU)
100
166
100
200
100
266
MHz
Memory bus frequency
33
83
33
100
33
133
MHz
PCI input frequency
25–66
MHz
Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral
logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configuration,for valid PLL_CFG[0:4] settings
and PCI_SYNC_IN frequencies.
Table 8. Clock AC Timing Specifications
At recommended operating conditions (see Table 2) with LVDD = 3.3 V ± 0.3 V
Num
Characteristics and Conditions
Min
Max
Unit
Notes
1
Frequency of operation (PCI_SYNC_IN)
25
66
MHz
2, 3
PCI_SYNC_IN rise and fall times
2.0
ns
1
4
PCI_SYNC_IN duty cycle measured at 1.4 V
40
60
%
5a
PCI_SYNC_IN pulse width high measured at 1.4 V
6
9
ns
2
5b
PCI_SYNC_IN pulse width low measured at 1.4 V
6
9
ns
2
7
PCI_SYNC_IN jitter
200
ps
8a
PCI_CLK[0:4] skew (pin-to-pin)
250
ps
8b
SDRAM_CLK[0:3] skew (pin-to-pin)
190
ps
3
10
Internal PLL relock time
100
s
2, 4, 5
15
DLL lock range with DLL_EXTEND = 0 (disabled) and
normal tap delay; (default DLL mode)
ns
6
16
DLL lock range for other modes
See Figure 8 through Figure 10
ns
6
17
Frequency of operation (OSC_IN)
25
66
MHz
19
OSC_IN rise and fall times
5
ns
7
20
OSC_IN duty cycle measured at 1.4 V
40
60
%
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