參數(shù)資料
型號(hào)： MPC755BRX300LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 6/48頁(yè)
文件大?。?/td> 1265K
代理商： MPC755BRX300LX
14
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Figure 5. AC Test Load
Figure 6 provides the input/output timing diagram for the MPC755.
Table 10. Processor Bus AC Timing Specifications 1
At recommended operating conditions (See Table 3)
Parameter
Symbols
300, 350, 400 MHz
Unit
Notes
Min
Max
Setup Times: All Inputs
tIVKH
2.5
—ns
Input Hold Times: TLBISYNC, MCP, SMI
tIXKH
0.6
—
ns
Input Hold Times: All Inputs, except TLBISYNC, MCP, SMI
tIXKH
0.2
—
ns
Valid Times: All Outputs
tKHOV
—4.1
ns
Output Hold Times: All Outputs
tKHOX
1.0
—
ns
SYSCLK to Output Enable
tKHOE
0.5
—
ns
2
SYSCLK to Output High Impedance (all except ABB,
ARTRY, DBB)
tKHOZ
—6.0
ns
2
SYSCLK to ABB, DBB High Impedance After Precharge
tKHABPZ
—1.0
t
sysclk
2, 3, 4
Maximum Delay to ARTRY Precharge
tKHARP
—1
t
sysclk
2, 3, 5
SYSCLK to ARTRY High Impedance After Precharge
tKHARPZ
—2
t
sysclk
2, 3, 5
Notes:
1. Revisions prior to Rev 2.8 (Rev E) were limited in performance and did not conform to this specification.
Contact your local Motorola sales office for more information.
2. Guaranteed by design and characterization.
3. tsysclk is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be
multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. Per the 60x bus protocol, TS, ABB and DBB are driven only by the currently active bus master. They are asserted
low then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for TS,
ABB or DBB is 0.5 x tSYSCLK, i.e. less than the minimum tSYSCLK period, to ensure that another master asserting
TS, ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is
tested for the signal asserted. Output valid time is tested for precharge.The high-Z behavior is guaranteed by
design.
5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately
following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any
master asserting it low in the first clock following AACK will then go to high-Z for one clock before precharging it
high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tsysclk;
i.e., it should be high-Z as shown in Figure 6 before the first opportunity for another master to assert ARTRY.
Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge.The
high-Z and precharge behavior is guaranteed by design.
OUTPUT
Z0 = 50
OVdd/2
RL = 50
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