參數(shù)資料
型號(hào)： MPC755BRX300LX
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝： 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁(yè)數(shù)： 10/48頁(yè)
文件大?。?/td> 1265K
代理商： MPC755BRX300LX
18
MPC755 RISC Microprocessor Hardware Specifications
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC755.
Figure 8. L2 Bus Input Timing Diagrams
Figure 9 shows the L2 bus output timing diagrams for the MPC755.
Output Hold Times
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOX
0.5
0.7
0.9
1.1
—
0.5
0.7
0.9
1.1
—
0.5
0.7
0.9
1.1
—
ns
3
L2SYNC_IN to High Impedance:
All outputs when L2CR[14-15] = 00
All outputs when L2CR[14-15] = 01
All outputs when L2CR[14-15] = 10
All outputs when L2CR[14-15] = 11
tL2CHOZ
—
2.4
2.6
2.8
3.0
—
2.4
2.6
2.8
3.0
—
2.4
2.6
2.8
3.0
ns
3, 5
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVdd.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the
rising edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint
of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive
50-ohm load (See Figure 10).
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous
BurstRAMs, L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs,
L2CR[14–15] = 11 is recommended.
5. Guaranteed by design and characterization.
6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact
your local Motorola sales office for more information.
Table 12. L2 Bus Interface AC Timing Specifications (Continued)
At recommended operating conditions (See Table 3)
Parameter
Symbol
300 MHz
350 MHz
400 MHz
Unit
Notes
Min
Max
Min
Max
Min
Max
L2SYNC_IN
L2 DATA AND DATA
VM
VM = Midpoint Voltage (L2OVDD/2)
tDVL2CH
tDXL2CH
tL2CR
tL2CF
PARITY INPUTS
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