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參數(shù)資料
| 型號： | MPC603E7TEC |
| 廠商： | Motorola, Inc. |
| 英文描述： | PowerPC 603e RISC Microprocessor |
| 中文描述： | RISC微處理器的PowerPC 603e |
| 文件頁數(shù)： | 24/36頁 |
| 文件大?。?/td> | 551K |
| 代理商： | MPC603E7TEC |
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PID7t-603e Hardware Specifications
System Design Information
1.8.2 PLL Power Supply Filtering
The AVdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop.
To ensure stability of the internal clock, the power supplied to the AVdd input signal should be Tltered using
a circuit similar to the one shown in Figure 13. The circuit should be placed as close as possible to the AVdd
pin to ensure it Tlters out as much noise as possible. The 0.1 μF capacitor should be closest to the AVdd pin,
followed by the 10 μF capacitor, and Tnally the 10
W
resistor to Vdd. These traces should be kept short and
direct.
Figure 13. PLL Power Supply Filter Circuit
1.8.3 Decoupling Recommendations
Due to the 603es dynamic power management feature, large address and data buses, and high operating
frequencies, the 603e can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other
components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power.
Therefore, it is recommended that the system designer place at least one decoupling capacitor at each Vdd
and OVdd pin of the 603e. It is also recommended that these decoupling capacitors receive their power from
separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
These capacitors should vary in value from 220 pF to 10
m
F to provide both high- and low-frequency
Tltering, and should be placed as close as possible to their associated Vdd or OVdd pin. Suggested values
for the Vdd pins220 pF (ceramic), 0.01 μF (ceramic), and 0.1 μF (ceramic). Suggested values for the
OVdd pins0.01 μF (ceramic), 0.1 μF (ceramic), and 10 μF (tantalum). Only SMT (surface mount
technology) capacitors should be used to minimize lead inductance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the Vdd and OVdd planes, to enable quick recharging of the smaller chip capacitors. These bulk
capacitors should also have a low ESR (equivalent series resistance) rating to ensure the quick response time
necessary. They should also be connected to the power and ground planes through two vias to minimize
inductance. Suggested bulk capacitors100 μF (AVX TPS tantalum) or 330 μF (AVX TPS tantalum).
1.8.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to Vdd. Unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the 603e.
Vdd
AVdd
10
W
10 μF
0
.
1 μF
GND
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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