
MOTOROLA
Chapter 11. L-Bus to U-Bus Interface (L2U)
11-7
Data Memory Protection
.
NOTE
The appropriate DMPU registers must be programmed before
the MSR[DR] bit is set. Otherwise, DMPU operation is not
guaranteed.
Program the region base address in the L2U_RBAx registers to the lower boundary of the
region specified by the corresponding L2U_RAx[RS] field. If the region base address does
not correspond to the boundary of the block size programmed in the L2U_RAx, the DMPU
snaps the region base to the lower boundary of that block. For example, if the block size is
programmed to 16 Kbytes for region zero (i.e., L2U_RA0[RS] = 0x3) and the region base
address is programmed to 0x1FFF(i.e., L2U_RBA0[RBA] = 0x1), then the effective base
Figure 11-3. Region Base Address Example
It requires external action to program only legal region sizes. The L2U does not check
whether the value is legal. If an illegal region size is programmed, the region calculation
may not be successful.
Table 11-1. DMPU Registers
Name
Description
L2U_RBA0
Region Base Address Register 0
L2U_RBA1
Region Base Address Register 1
L2U_RBA2
Region Base Address Register 2
L2U_RBA3
Region Base Address Register 3
L2U_RA0
Region Attribute Register 0
L2U_RA1
Region Attribute Register 1
L2U_RA2
Region Attribute Register 2
L2U_RA3
Region Attribute Register 3
L2U_GRA
Global Region Attribute
Region 0
(16 Kbytes)
Actual Programmed Region
Resulting Region
0x0000 0000
0x0000 1FFF
0x0000 3FFF
0x0000 5FFF