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MOTOROLA
Chapter 3. Central Processing Unit
3-45
User Instruction Set Architecture (UISA)
Fixed-point rotate and shift instructions
Move to/from system register instructions
All instructions are defined for the fixed-point processor in the UISA in the hardware. For
performance of the various instructions, refer to
Table 3-22.— Move To/From System Register Instructions. Move to/from invalid special
registers in which SPR0 = 1 yields invocation of the privilege instruction error
interrupt handler if the processor is in problem state. For a list of all implemented
Fixed-Point Arithmetic Instructions. If an attempt is made to perform any of the divisions
in the divw[o][.] instruction (0x80000000
÷ -1, <anything> ÷ 0), then the contents of RT
are 0x80000000; if Rc =1, the contents of bits in CR field 0 are LT = 1, GT = 0, EQ = 0, and
SO is set to the correct value. If an attempt is made to perform any of the divisions in the
divw[o][.] instruction, <anything>
÷ 0. In cmpi, cmp, cmpli, and cmpl instructions, the
L-bit is applicable for 64-bit implementations. In 32-bit implementations, if L = 1 the
instruction form is invalid. The core ignores this bit and therefore, the behavior when L =
1 is identical to the valid form instruction with L = 0
3.13.9 Floating-Point Processor
3.13.9.1 General
The MPC565/MPC566 implements all floating-point features as defined in the UISA,
including the non-IEEE working mode. Some features require software assistance. For
more information refer to the RCPU Reference Manual (Floating-point Load Instructions)
for more information.
3.13.9.2 Optional instructions
The only optional instruction implemented by MPC565/MPC566 hardware is store
floating-point as integer word indexed (stfiwx). An attempt to execute any other optional
instruction causes an implementation dependent software emulation interrupt.
3.13.10Load/Store Processor
The load/store processor supports all of the 32-bit implementation fixed-point MPC500
load/store instructions in the hardware.
3.13.10.1 Fixed-Point Load With Update and Store With Update
Instructions
For load with update and store with update instructions, when RA = 0, the EA is written
into R0. For load with update instructions, when RA = RT, RA is boundedly undefined.