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參數(shù)資料
| 型號(hào)： | MPC5646CF0VMJ8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MAPBGA-256 |
| 文件頁(yè)數(shù)： | 83/115頁(yè) |
| 文件大小： | 783K |
| 代理商： | MPC5646CF0VMJ8 |
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Block diagram
MPC5646C Microcontroller Datasheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
7
Table 2 summarizes the functions of the blocks present on the MPC5646C.
Table 2. MPC5646C series block summary
Block
Function
Analog-to-digital converter (ADC) Converts analog voltages to digital values
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Cryptographic Security Engine
(CSE)
Supports the encoding and decoding of any kind of data
Crossbar (XBAR) switch
Supports simultaneous connections between two master ports and three slave
ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width
DMA Channel Multiplexer
(DMAMUX)
Allows to route DMA sources (called slots) to DMA channels
Deserial serial peripheral interface
(DSPI)
Provides a synchronous serial interface for communication with external devices
Error Correction Status Module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset status
register, wakeup control for exiting sleep modes, and optional features such as
information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access
(eDMA)
Performs complex data transfers with minimal intervention from a host processor
via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area network) Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
FlexRay (FlexRay communication
controller)
Provides high-speed distributed control for advanced automotive applications
Fast Ethernet Controller (FEC)
Ethernet Media Access Controller (MAC) designed to support both 10 and 100
Mbps Ethernet/IEEE 802.3 networks
Internal multiplexer (IMUX) SIUL
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C) bus A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests for both
e200z0h and e200z4d cores
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
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