參數(shù)資料
型號(hào)： MPC5646CF0VMJ8
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù)： 67/115頁(yè)
文件大?。?/td> 783K
代理商： MPC5646CF0VMJ8
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Electrical Characteristics
MPC5646C Microcontroller Datasheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
55
EMI/decoupling cap (CREGP) at each VDD_LV/VSS_LV pin pair.
4.8.1.1
Recommendations
The external NPN driver must be BCP68 type.
VDD_LV should be implemented as a power plane from the emitter of the ballast transistor.
10
F capacitors should be connected to the 4 pins closest to the outside of the package and should be evenly
distributed around the package. For BGA packages, the balls should be used are D8, H14, R9, J3–one cap on each side
of package.
— There should be a track direct from the capacitor to this pin (pin also connects to VDD_LV plane). The tracks ESR
should be less than 100 m
.
— The remaining VDD_LV pins (exact number will vary with package) should be decoupled with 0.1 F caps,
connected to the pin as per 10
F.
4.8.2
VDD_BV options
Option 1: VDD_BV shared with VDD_HV_A
VDD_BV must be star routed from VDD_HV_A from the common source. This is to eliminate ballast noise injection on
the MCU.
Option 2: VDD_BV independent of the MCU supply
VDD_BV > 2.6 V for correct functionality. The device is not monitoring this supply hence the external component must
meet the 2.6 V criteria through external monitoring if required.
Table 22. Voltage regulator electrical characteristics
Symbol
C
Parameter
Conditions1
Value2
Unit
Min
Typ
Max
CREGn
SR — External ballast stability capacitance
—
40
—
60
F
RREG
SR — Stability capacitor equivalent serial
resistance
——
—
0.2
CREGP
SR — Decoupling capacitance (Close to
the pin)
VDD_HV_A/HV_B/VSS_HV
pair
100
—
nF
VDD_LV/VSS_LV pair
100
—
nF
CDEC2
SR — Stability capacitance regulator
supply (Close to the ballast collector)
VDD_HV_A/VSS_HV
10
—
40
F
VMREG
CC P Main regulator output voltage
Before trimming
—
1.32
—
V
After trimming
—
1.28
—
IMREG
SR — Main regulator current provided to
VDD_LV domain
——
—
350
mA
IMREGINT
CC D Main regulator module current
consumption
IMREG = 200 mA
—
2
mA
IMREG = 0 mA
—
1
VLPREG
CC P Low power regulator output voltage
After trimming
—
1.23
—
V
ILPREG
SR — Low power regulator current
provided to VDD_LV domain
—
——
50
mA
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