參數(shù)資料
型號(hào): MPC5646CF0VMJ1R
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 120 MHz, MICROCONTROLLER, PBGA256
封裝: 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MAPBGA-256
文件頁(yè)數(shù): 94/115頁(yè)
文件大?。?/td> 783K
代理商: MPC5646CF0VMJ1R
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MPC5646C Microcontroller Datasheet, Rev. 4
Preliminary—Subject to Change Without Notice
Block diagram
Freescale Semiconductor
8
LinFlexD (Local Interconnect
Network Flexible with DMA
support)
Manages a high number of LIN (Local Interconnect Network protocol) messages
efficiently with a minimum of CPU load
Memory protection unit (MPU)
Provides hardware access control for all memory references generated in a
device
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Reset generation module
(MC_RGM)
Centralizes reset sources and manages the device reset sequence of the device
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and
modetransition sequences in all functional states; also manages the power
control unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Non-Maskable Interrupt (NMI)
Handles external events that must produce an immediate response, such as
power down detection
Nexus Development Interface
(NDI)
Provides real-time development capabilities for e200z0h and e200z4d core
processor
Periodic interrupt timer/ Real Time
Interrupt Timer (PIT_RTI)
Produces periodic interrupts and triggers
Real-time counter (RTC/API)
A free running counter used for time keeping applications, the RTC can be
configured to generate an interrupt at a predefined interval independent of the
mode of operation (run mode or low-power mode). Supports autonomous
periodic interrupt (API) function to generate a periodic wakeup request to exit a
low power mode or an interrupt request
Static random-access memory
(SRAM)
Provides storage for program code, constants, and variables
System integration unit lite (SIUL) Provides control over all the electrical pad controls and up 32 ports with 16 bits
of bidirectional, general-purpose input and output signals and supports up to 32
external interrupts with trigger event configuration
System status and configuration
module (SSCM)
Provides system configuration and status data (such as memory size and status,
device mode and security status), device identification data, debug status port
enable and selection, and bus and peripheral abort enable/disable
System timer module (STM)
Provides a set of output compare events to support AutoSAR and operating
system tasks
Semaphores
Provides the hardware support needed in multi-core systems for sharing
resources and provides a simple mechanism to achieve lock/unlock operations
via a single write access.
Wake Unit (WKPU)
Supports external sources that can generate interrupts or wakeup events, of
which can cause non-maskable interrupt requests or wakeup events.
Table 2. MPC5646C series block summary (continued)
Block
Function
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