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| 型號(hào)： | MPC5646CF0VMJ1R |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 120 MHz, MICROCONTROLLER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MAPBGA-256 |
| 文件頁(yè)數(shù)： | 88/115頁(yè) |
| 文件大?。?/td> | 783K |
| 代理商： | MPC5646CF0VMJ1R |
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MPC5646C Microcontroller Datasheet, Rev. 4
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
74
A second aspect involving the capacitance network shall be considered. Assuming the three capacitances CF, CP1 and CP2 are
initially charged at the source voltage VA (refer to the equivalent circuit reported in Figure 16): A charge sharing phenomenon
is installed when the sampling phase is started (A/D switch close).
Figure 18. Transient behavior during sampling phase
In particular two different transient periods can be distinguished:
1.
A first and quick charge transfer from the internal capacitance CP1 and CP2 to the sampling capacitance CS occurs (CS
is supposed initially completely discharged): considering a worst case (since the time constant in reality would be
faster) in which CP2 is reported in parallel to CP1 (call CP = CP1 + CP2), the two capacitances CP and CS are in series,
and the time constant is
Eqn. 5
Equation 5 can again be simplified considering only CS as an additional worst condition. In reality, the transient is
faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time TS
is always much longer than the internal time constant:
Eqn. 6
The charge of CP1 and CP2 is redistributed also on CS, determining a new value of the voltage VA1 on the capacitance
according to Equation 7:
Eqn. 7
2.
A second charge transfer involves also CF (that is typically bigger than the on-chip capacitance) through the resistance
RL: again considering the worst case in which CP2 and CS were in parallel to CP1 (since the time constant in reality
would be faster), the time constant is:
Eqn. 8
In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed
well before the end of sampling time TS, a constraints on RL sizing is obtained:
VA
VA1
VA2
t
TS
VCS
Voltage Transient on CS
V <0.5 LSB
1
2
1 < (RSW + RAD) CS << TS
2 = RL (CS + CP1 + CP2)
1
R
SW
R
AD
+
=
C
P
C
S
C
P
C
S
+
---------------------
1
R
SW
R
AD
+
C
S
T
S
V
A1
C
S
C
P1
C
P2
++
V
A
C
P1
C
P2
+
=
2
R
L
C
S
C
P1
C
P2
++
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