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| 型號(hào)： | MPC5646CF0CMJ8 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, MICROCONTROLLER, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, MAPBGA-256 |
| 文件頁(yè)數(shù)： | 96/115頁(yè) |
| 文件大?。?/td> | 783K |
| 代理商： | MPC5646CF0CMJ8 |
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Electrical Characteristics
MPC5646C Microcontroller Datasheet, Rev. 4
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
81
4.18
Fast Ethernet Controller
MII signals use CMOS signal levels compatible with devices operating at 3.3 V. Signals are not TTL compatible. They follow
the CMOS electrical characteristics.
4.18.1
MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)
The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequency
requirement. In addition, the system clock frequency must exceed four times the RX_CLK frequency in 2:1 mode and two times
the RX_CLK frequency in 1:1 mode.
Figure 21. MII receive signal timing diagram
6 During the sample time the input capacitance C
S can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within tADC1_S. After the
end of the sample time tADC1_S, changes of the analog input voltage have no effect on the conversion result. Values
for the sample clock tADC1_S depend on programming.
7 Conversion time = Bit evaluation time + Sampling time + 1 Clock cycle delay.
8 Refer to ADC conversion table for detailed calculations.
9 Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a
combination of Offset, Gain and Integral Linearity errors.
Table 44. MII Receive Signal Timing
Spec
Characteristic
Min
Max
Unit
M1
RXD[3:0], RX_DV,
RX_ER to RX_CLK
setup
5—
ns
M2
RX_CLK to
RXD[3:0], RX_DV,
RX_ER hold
5—
ns
M3
RX_CLK pulse width
high
35%
65%
RX_CLK period
M4
RX_CLK pulse width
low
35%
65%
RX_CLK period
M1
M2
RX_CLK (input)
RXD[3:0] (inputs)
RX_DV
RX_ER
M3
M4
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