
CAN 2.0B Controller Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
16-9
information on the bit timing registers.
Figure 16-5. Relationship between System Clock and CAN Bit Segments
A bit is divided into four separate non-overlapping time segments called SYNC_SEG, PROPSEG, PSEG1,
and PSEG2. These are illustrated in
Figure 16-5. The period of the nominal bit time (NBT) is the sum of
the segment durations:
t
NBT = t SYNC_SEG + t PROPSEG + t PSEG1 + t PSEG2
The sample point indicated in
Figure 16-5 is the position of the actual sample point if a single sample per
bit is selected (CANCTRL1[SAMP] bit = 0). If three samples per bit are selected, the sample point
indicated in
Figure 16-5 marks the position of the final sample.
Table 16-8. Example System Clock, CAN Bit Rate, and S-Clock Frequencies
System Clock
Frequency
(MHz)
CAN Bit Rate
(MHz)
Possible S-Clock
Frequency (MHz)
Possible Number of
Time Quanta/Bit
PRESDIV Value + 1
56
1
56
1
40
1
40
1
25
1
25
1
20
1
10, 20
2, 1
16
1
8, 16
2, 1
56
0.500
56
118
1
40
0.500
40
80
1
25
0.500
25
50
1
20
0.500
1, 2, 2.5
2, 4, 5
20, 10, 8
SYSTEM
CLOCK
S-CLOCK
TIME
QUANTUM
SYNC_SEG
Nominal bit time (NBT)
Sample point
PROPSEG
PSEG1
PSEG2
Transmit
point
Baud Rate Prescaler (PRESDIV)
SS