參數(shù)資料
型號： MPC5607BVLL4R
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： FLASH, 48 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, MS-026 BED, LQFP-100
文件頁數(shù)： 54/106頁
文件大?。?/td> 667K
代理商： MPC5607BVLL4R
Electrical characteristics
MPC5607B Microcontroller Data Sheet, Rev. 5
Freescale Semiconductor
51
4.8
Power management electrical characteristics
4.8.1
Voltage regulator electrical characteristics
The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage
ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved:
HV: High voltage external power supply for voltage regulator module. This must be provided externally through VDD
power pin.
BV: High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV
power pin. Voltage values should be aligned with VDD.
LV: Low voltage internal power supply for core, FMPLL and Flash digital logic. This is generated by the internal
voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure
noise isolation between critical LV modules within the device:
— LV_COR: Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.
— LV_CFLA: Low voltage supply for code Flash module. It is supplied with dedicated ballast and shorted to
LV_COR through double bonding.
Ttr
CC D Output transition time output
pin3 MEDIUM configuration
CL = 25 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
—
10
ns
CL = 50 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
20
CL = 100 pF,
VDD = 5.0 V ± 10%, PAD3V5V = 0
——
40
CL = 25 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
12
CL = 50 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
25
CL = 100 pF,
VDD = 3.3 V ± 10%, PAD3V5V = 1
——
40
WFRST SR P RESET input filtered pulse
—
40
ns
WNFRST SR P RESET input not filtered pulse
—
1000
—
ns
|IWPU| CC P Weak pull-up current absolute
value
VDD = 3.3 V ± 10%, PAD3V5V = 1
10
—
150
A
VDD = 5.0 V ± 10%, PAD3V5V = 0
10
—
150
VDD = 5.0 V ± 10%, PAD3V5V = 1
4
10
—
250
1 V
DD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to 125 °C, unless otherwise specified
2 This is a transient configuration during power-up, up to the end of reset PHASE2 (refer to RGM module section of
the device reference manual).
3 C
L includes device and package capacitance (CPKG <5pF).
4 The configuration PAD3V5 = 1 when V
DD = 5 V is only transient configuration during power-up. All pads but RESET
and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.
Table 20. Reset electrical characteristics (continued)
Symbol
C
Parameter
Conditions1
Value
Unit
Min
Typ
Max
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