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參數資料
| 型號： | MPC5567EVB |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 55/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION MPC5567MZP132 |
| 標準包裝： | 1 |
| 類型： | 微控制器 |
| 適用于相關產品： | MPC5567MZP132 |
| 所含物品： | 評估板 |
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Revision History for the MPC5567 Data Sheet
MPC5567 Microcontroller Data Sheet, Rev. 2
Freescale
59
The following table describes the changes made to information in tables and figures, and is presented in
sequential page number order.
First paragraph, text changed from “. . . based on the PowerPC Book E architecture” to “. . . built on the Power
Architecture embedded technology.”
Second paragraph: Changed terminology from PowerPC Book E architecture to Power Architecture terminology.
Added new fourth paragraph about VLE feature.
Added the VLE paragraph.
Added paragraph about the Fast Ethernet Controller directly after the System Integration Unit paragraph.
Added paragraph about the FlexRay Controller directly after the Fast Ethernet Controller paragraph.
Added the sentence directly preceding Table 1: ‘Unless noted in this data sheet, all specifications apply
from TL to TH.’
Sections 3.7.1, 3.7.2 and 3.7.3: Reordered sections resulting in the following order and section renumbering:
From: ‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
(1s) when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6) when powering the device
by more than the VDD33 lag specification in Table 6. VDD33 individually can lag either VDDSYN or the RESET power
pin (VDDEH6) by more than the VDD33 lag specification. VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but
cannot lag both by more than the VDD33 lag specification. This VDD33 lag specification only applies during power
up. VDD33 has no lead or lag requirements when powering down.’
To:
‘When powering the device, VDD33 must not lag VDDSYN and the RESET power pin (VDDEH6) by more than the
VDD33 lag specification listed in Table 6. This avoids accidentally selecting the bypass clock mode because the
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state when
POR negates. VDD33 can lag VDDSYN or the RESET power pin (VDDEH6), but cannot lag both by more than the
VDD33 lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.’
Added the following text directly before this section and after Table 8 Pin Status for Medium / Slow Pads During the
Power-on Sequence:
‘The values in Table 7 and Table 8 do not include the effect of the weak pull devices on the output pins during
power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When
the internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up or
down) are enabled as defined in the device Reference Manual. If VDD is too low to correctly propagate the logic
signals, the weak-pull devices can pull the signals to VDDE and VDDEH.
To avoid this condition, minimize the ramp time of the VDD supply to a time period less than the time required to
enable the external circuitry connected to the device outputs.’
Section 3.7.3, “Power-Down Sequence (VRC33 Grounded)” Deleted the underscore in ORed_POR to become ORed POR.
Table 34. Global and Text Changes Between Rev. 0.0 and 1.0 (continued)
Location
Description of Change
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MPC5567EVBE | 功能描述:BOARD EVALUATION MPC5567 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:- 產品培訓模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產品:Blackfin? BF50x Series Processors 標準包裝:1 系列:Blackfin® 類型:DSP 適用于相關產品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關產品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| MPC5567MVR112 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MVR112R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
| MPC5567MVR132 | 制造商:Freescale Semiconductor 功能描述: 制造商:Freescale Semiconductor 功能描述:2MB FLASH W/ECC, 5 CANS - Trays |
| MPC5567MVR132R2 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontroller |
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