參數(shù)資料
型號(hào)： MPC5534MVF40
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 12/50頁(yè)
文件大小： 1148K
代理商： MPC5534MVF40
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
12
the internal 3.3-V POR or the RESET power POR must be depended on to hold the device in reset. Since
they may negate as low as 2.0 V, it is necessary for VDD to be within spec before the 3.3-V POR and the
RESET POR negate.
Figure 2. Power Up Sequence if VRC33 Grounded
3.7.2
Power Down Sequence (If VRC33 Grounded)
In this case, the only requirement is that if VDD falls below its operating range, VDDSYN or the RESET
power must fall below 2.0 V before VDD is allowed to rise back into its operating range. This ensures that
digital 1.5-V logic that is only reset by ORed_POR, which may have been affected by the 1.5V supply
falling below spec, is reset properly.
3.7.3
Input Value of Pins During POR Dependent on VDD33
In order to avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not
treated as 1s when POR negates, VDD33 must not lag VDDSYN and the RESET pin power (VDDEH6)
when powering the device by more than the VDD33 lag specification in
Table 6
. VDD33 individually can
lag either VDDSYN or the RESET pin power (VDDEH6) by more than the VDD33 lag specification.
VDD33 can lag one of the VDDSYN or VDDEH6 supplies, but cannot lag both by more than the VDD33
lag specification. This VDD33 lag specification only applies during power up. VDD33 has no lead or lag
requirements when powering down.
3.8
DC Electrical Specifications
Table 9. DC Electrical Specifications
Num
Characteristic
Symbol
Min
Max
Unit
1
Core Supply Voltage (average DC RMS voltage)
V
DD
1.35
1.65
V
2
I/O Supply Voltage (Fast I/O)
V
DDE
1.62
3.6
V
3
I/O Supply Voltage (Slow/Medium I/O)
V
DDEH
3.0
5.25
V
4
3.3V I/O Buffer Voltage
V
DD33
3.0
3.6
V
5
Voltage Regulator Control Input Voltage
V
RC33
3.0
3.6
V
VDDSYN and RESET Power
VDD
2.0V
1.35V
VDD must reach 1.35V before VDDSYN and the RESET power reach 2.0V
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