參數(shù)資料
型號(hào)： MPC5534AZQ66R2
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 44/50頁(yè)
文件大?。?/td> 1148K
代理商： MPC5534AZQ66R2
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Electrical Characteristics
Freescale Semiconductor
44
3.13.9
eQADC SSI Timing
Figure 27. EQADC SSI Timing
Table 27. EQADC SSI Timing Characteristics (pads at 3.3V or at 5.0V)
1
1
SS timing specified at F
SYS
= 80MHz, VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, T
A
= TL to TH, and CL = 50pF with SRC = 0b11.
2
Maximum operating frequency is highly dependent on track delays, master pad delays, and slave pad delays.
3
FCK duty is not 50% when it is generated through the division of the system clock by an odd number.
CLOAD = 25pF on all outputs. Pad drive strength set to maximum.
Num
Rating
Symbol
Min
Typ
Max
Unit
1
FCK Frequency
2, 3
f
FCK
t
FCK
t
FCKHT
t
FCKLT
t
SDS_LL
t
SDO_LL
t
EQ
_
SU
t
EQ_HO
1/17
—
1
/
2
f
SYS_CLK
t
SYS_CLK
ns
2
FCK Period (t
FCK
= 1/ f
FCK
)
Clock (FCK) High Time
2
—
17
3
t
SYS_CLK
6.5
t
SYS_CLK
6.5
–7.5
—
9* t
SYS_CLK
+
6.5
8* t
SYS_CLK
+
6.5
+7.5
4
Clock (FCK) Low Time
—
ns
5
SDS Lead/Lag Time
—
ns
6
SDO Lead/Lag Time
–7.5
—
+7.5
ns
7
EQADC Data Setup Time (Inputs)
22
—
—
ns
8
EQADC Data Hold Time (Inputs)
1
—
—
ns
1st (MSB)
2nd
25th
26th
1st (MSB) 2nd
25th
26th
8
7
5
6
4
5
4
2
3
FCK
SDS
SDO
External Device Data Sample at
FCK Falling Edge
SDI
EQADC Data Sample at
FCK Rising Edge
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