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參數(shù)資料
| 型號： | MPC5534AZQ66R2 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 21/50頁 |
| 文件大?。?/td> | 1148K |
| 代理商： | MPC5534AZQ66R2 |
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Electrical Characteristics
MPC5534 Microcontroller Data Sheet, Rev. 0
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
21
4
Resolution
3
—
1.25
—
mV
5
INL: 6 MHz ADC Clock
INL6
–4
4
Counts
3
6
INL: 12 MHz ADC Clock
INL12
–8
–3
4
–6
4
–4
5
–8
6
8
Counts
7
DNL: 6 MHz ADC Clock
DNL6
3
4
6
4
4
5
8
6
Counts
8
DNL: 12 MHz ADC Clock
DNL12
Counts
9
Offset Error with Calibration
OFFWC
Counts
10
Full Scale Gain Error with Calibration
Disruptive Input Injection Current
7, 8, 9, 10
GAINWC
Counts
11
I
INJ
E
INJ
–1
1
mA
12
Incremental Error due to injection current. All channels have
same 10k
< Rs <100k
Channel under test has Rs=10k
,
I
INJ
=I
INJMAX
,I
INJMIN
Total Unadjusted Error for single ended conversions with
calibration
11, 12,
13, 14, 15
–4
4
Counts
13
TUE
–4
4
Counts
1
Conversion characteristics vary with F
ADCLK
rate. Reduced conversion accuracy occurs at maximum F
ADCLK
rate. The
maximum value is based on 800KS/s and the minimum value is based on 20MHz oscillator clock frequency divided by a
maximum 16 factor.
2
Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that
the ADC is ready to perform conversions.
3
At VRH – VRL = 5.12 V, one lsb = 1.25 mV = one count
4
Guaranteed 10-bit monotonicity
5
The absolute value of the offset error without calibration
≤
100 counts.
6
The absolute value of the full scale gain error without calibration
≤
120 counts.
7
Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater than
V
RH
and 0x000 for values less than V
RL
. This assumes that V
RH
≤
V
DDA
and V
RL
≥
V
SSA
due to the presence of the sample
amplifier. Other channels are not affected by non-disruptive conditions.
8
Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do
not affect device reliability or cause permanent damage.
9
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values using V
POSCLAMP
= V
DDA
+ 0.5V and V
NEGCLAMP
= – 0.3 V, then use the larger of the calculated values.
10
Condition applies to two adjacent pads on the internal pad.
11
The TUE specification will always be better than the sum of the INL, DNL, offset, and gain errors due to canceling errors.
12
TUE does not apply to differential conversions.
13
Measured at 6 MHz ADC clock. TUE with a 12 MHz ADC clock is: –16 counts < TUE < 16 counts.
14
TUE includes all internal device error such as internal reference variation (75% Ref, 25% Ref)
15
Depending on the customer input impedance, the Analog Input Leakage current (DC Electrical specification 35a) may affect
the actual TUE measured on analog channels AN12, AN13, AN14, AN15.
Table 13. eQADC Conversion Specifications (Operating) (continued)
Num
Characteristic
Symbol
Min
Max
Unit
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