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| 型號(hào)： | MPC184VMB |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SECURITY PROCESSOR 252-MAPBGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 處理器類(lèi)型： | MPC1xx PowerPC ISA PCI 橋/存儲(chǔ)器 |
| 速度： | 66MHz |
| 電壓： | 1.5V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 252-BGA |
| 供應(yīng)商設(shè)備封裝： | 252-MAPBGA（21x21） |
| 包裝： | 托盤(pán) |
4
MPC184 Security Processor Technical Summary
MOTOROLA
5 Architectural Overview
A block diagram of the MPC184 internal architecture is shown in Figure 5-3. The mode selectable 8xx/PCI
bus interface module is designed to transfer 32-bit words between the external bus and any register inside
the MPC184. An operation begins with a write of a pointer to a crypto-channel fetch register which points
to a data packet descriptor. The channel then requests the descriptor and decodes the operation to be
performed. The channel then makes requests of the controller to assign crypto execution units and fetch the
keys, IV’s and data needed to perform the given operation. The controller satises the requests by assigning
execution units to the channel and by making requests to the master interface per the programmable priority
scheme. As data is processed, it is written to the individual execution units output buffer and then back to
system memory via the bus interface module.
Figure 5-3. MPC184 Functional Blocks
6
Data Packet Descriptors
As an IPSec accelerator, the MPC184’s controller has been designed for easy use and integration with
existing systems and software. All cryptographic functions are accessible through data packet descriptors,
some of which have been dened as multifunction to facilitate IPSec applications. A data packet descriptor
is diagrammed in Table 6-1.
Table 6-1. Example Data Packet Descriptor
Field Name
Value/Type
Description
DPD_DES_CTX_CRYPT
tbd
Representative header for DES using Context to Encrypt
LEN_CTXIN
PTR_CTXIN
length
pointer
Number of bytes to be written
Pointer to Context (IV) to be written into DES engine
LEN_KEY
PTR_KEY
length
pointer
Number of bytes in key
Pointer to block cipher key
LEN_DATAIN
PTR_DATAIN
length
pointer
Number of bytes of data to be ciphered
Pointer to data to perform cipher upon
LEN_DATAOUT
PTR_DATAOUT
length
pointer
Number of bytes of data after ciphering
Pointer to location where cipher output is to be written
crypto-
channel
crypto-
channel
crypto-
channel
crypto-
channel
Master/slave
interface
Control
PKEU
DEU
FIFO
RNG
FIFO
AESU
8KB
gpRAM
FIFO
MDEU
FIFO
AFEU-4
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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