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| 型號： | MPC184VMB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SECURITY PROCESSOR 252-MAPBGA |
| 標準包裝： | 60 |
| 處理器類型： | MPC1xx PowerPC ISA PCI 橋/存儲器 |
| 速度： | 66MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 252-BGA |
| 供應(yīng)商設(shè)備封裝： | 252-MAPBGA（21x21） |
| 包裝： | 托盤 |
MOTOROLA
MPC184 Security Processor Technical Summary
7
Crypto-channels analyze the data packet descriptor header and request from the controller the rst required
cryptographic service. The controller implements a programmable prioritization scheme that allows the user
to dictate the order in which the four crypto-channels are serviced. After the controller grants access to the
required EU, the crypto-channel and the controller perform the following steps:
1. Set the appropriate Mode bits available in the EU for the required service.
2. Fetch context and other parameters as indicated in the data packet descriptor buffer and use these
to program the EU.
3. Fetch data as indicated and place in either the EU’s input FIFO or the EU itself (as appropriate).
4. Wait for EU to complete processing.
5. Upon completion, unload results and context and write them to external memory as indicated by
the data packet descriptor buffer.
6. If multiple services requested, go back to step 2.
7. Reset the appropriate EU if it is dynamically assigned. Note that if statically assigned, a EU is
reset only upon direct command written to the MPC184.
8. Perform descriptor completion notication as appropriate. This notication comes in one of two
forms—interrupt or header writeback modication—and can occur either at the end of every
descriptor or at the end of a descriptor chain.
7 Execution Units (EUs)
“Execution unit” is the generic term for a functional block that performs the mathematical permutations
required by protocols used in cryptographic processing. The EUs are compatible with IPsec, WAP/WTLS,
IKE, SSL/TLS and 802.11i processing, and can work together to perform high level cryptographic tasks.The
MPC184’s execution units are as follows:
PKEU for computing asymmetric key mathematics, including Modular Exponentiation (and other
Modular Arithmetic functions) or ECC Point Arithmetic
DEU for performing block symmetric cryptography using DES and 3DES
AFEU for performing RC-4 compatible stream symmetric cryptography
AESU for performing the Advanced Encryption Standard algorithm
MDEU for hashing data
RNG for random number generation
7.1 Public Key Execution Unit (PKEU)
The PKEU is capable of performing many advanced mathematical functions to support both RSA and ECC
public key cryptographic algorithms. ECC is supported in both F(2)m (polynomial-basis) and F(p) modes.
This EU supports all levels of functions to assist the host microprocessor to perform its desired
cryptographic function. For example, at the highest level, the accelerator performs modular exponentiations
to support RSA and performs point multiplies to support ECC. At the lower levels, the PKEU can perform
simple operations such as modular multiplies.
7.1.1 Elliptic Curve Operations
The PKEU has its own data and control units, including a general-purpose register le in the
programmable-size arithmetic unit. The eld or modulus size can be programmed to any value between 160
bits and 512 bits in programmable increments of 8, with each programmable value i supporting all actual
eld sizes from i*8 -7 to i*8. The result is hardware supporting a wide range of cryptographic security.
Larger eld / modulus sizes result in greater security but lower performance; processing time is determined
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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