
D-4
MPC106 PCIB/MC User's Manual
MOTOROLA
;#
lis r3, MPC106_REG # start building new register number
ori r3, r3, ALT_OSV_1 # register number 0xba
stwbrx r3, 0, r1 # write this value to CONFIG_ADDR
lbz r4, 2(r2) # load r4 from CONFIG_DATA
lis r0, 0x0000 #
ori r0, r0, 0x0026 #
or r4, r4, r0 # sets the desired bits
stb r4, 2(r2) # write the modified data to CONFIG_DATA
;#
lis r3, MPC106_REG # start building new register number
ori r3, r3, ALT_OSV_2 # register number 0xbb
stwbrx r3, 0, r1 # write this value to CONFIG_ADDR
lbz r4, 3(r2) # load r4 from CONFIG_DATA
lis r0, 0x0000 #
ori r0, r0, 0x0000 #
or r4, r4, r0 # sets the desired bits
stb r4, 3(r2) # write the modified data to CONFIG_DATA
;#=====================================================================================
;#
;# This section of code initializes the MPC106's memory configuration registers
;# for use with the MDC2 (64 MB PDRAM/EDO and 2 MB SRAM BootROM) at 60 - 66 MHz.
;#
;# This will branch to either initmdc2pdram for page mode type dram or
;# it will branch to initmdc2edo for edo dram
b WHICHDRAM
;#
;#************************Normal page mode DRAM initialization****************
initmdc2pdram:
;#
lis r3, MPC106_REG # start building new register number
ori r3, r3, MCCR1 # register number 0xf0
stwbrx r3, 0, r1 # write this value to CONFIG_ADDR
;#
lwbrx r4, 0, r2 # load r4 from CONFIG_DATA
lis r0, 0x0016 # REDUCE WAIT STATES FOR ROM ACCESSES
ori r0, r0, 0x5555 # (contains no reserved bits)
and r4, r4, r0 # clears the desired bits
or r4, r4, r0 # sets the desired bits
stwbrx r4, 0, r2 # write the modified data to CONFIG_DATA
;#
lis r3, MPC106_REG # start building new register number