
3-44
MPC106 PCIB/MC User's Manual
MOTOROLA
16
PCKEN
0
Memory interface parity checking/generation enable
0
Disables parity checking and parity generation for
transactions to DRAM/EDO/SDRAM memory. If ECC is
enabled, disables L2 parity checking.
1
Enables parity checking and generation for all memory
transactions to DRAM/EDO/SDRAM. If ECC is enabled,
enables L2 parity checking.
15–14
Bank 7 row
00
RAM bank 7 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 7.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
13–12
Bank 6 row
00
RAM bank 6 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 6.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
11–10
Bank 5 row
00
RAM bank 5 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 5.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
9–8
Bank 4 row
00
RAM bank 4 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 4.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
7–6
Bank 3 row
00
RAM bank 3 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 3.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
5–4
Bank 2 row
00
RAM bank 2 row address bit count. These bits indicate the
number of row address bits that are required by the RAM devices
in bank 2.
00 9 row bits
01 10 row bits
10 11 row bits
11 12 or 13 row bits
Table 3-31. Bit Settings for MCCR1—0xF0 (Continued)
Bit
Name
Reset
Value
Description