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參數(shù)資料
| 型號： | MMK2-67025EV-30 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | Static RAM |
| 英文描述： | 8K X 16 DUAL-PORT SRAM, 30 ns, QFP84 |
| 封裝： | MQFP-84 |
| 文件頁數(shù)： | 22/23頁 |
| 文件大?。?/td> | 355K |
| 代理商： | MMK2-67025EV-30 |
M67025E
Rev. G – July 6, 2000
8
Table 3 : Interrupt Flag (1, 4).
LEFT PORT
RIGHT PORT
R/WL
CSL
OEL
AOL–A12L
INTL
R/WR
CSR
OER
AOR–A12R
INTR
FUNCTION
L
X
1FFF
X
L(2)
Set Right INTR Flag
X
L
1FFF
H(3)
Reset Right INTR Flag
X
L(3)
L
X
1FFE
X
Set Left INTL Flag
X
L
1FFE
H(2)
X
Reset Left INTL Flag
Notes :
1. Assumes BUSYL = BUSYR = H.
2. If BUSYL = L, then NC.
3. If BUSYR = L, then NC.
4. H = HIGH, L = LOW, X = DON’T CARE, NC = NO CHANGE.
Table 4 : Arbitration (2)
LEFT PORT
RIGHT PORT
FLAGS (1)
CSL
A0L – A12L
CSR
A0R – A12R
BUSYL
BUSYR
FUNCTION
H
X
H
X
H
No Contention
L
Any
H
X
H
No Contention
H
X
L
Any
H
No Contention
L
≠ A0R – A12R
L
≠ A0L – A12L
H
No Contention
ADDRESS ARBITRATION WITH CS LOW BEFORE ADDRESS MATCH
L
LV5R
L
LV5R
H
L
L–Port Wins
L
RV5L
L
RV5L
L
H
R–Port Wins
L
Same
L
Same
H
L
Arbitration Resolved
L
Same
L
Same
L
H
Arbitration Resolved
CS ARBITRATION WITH ADDRESS MATCH BEFORE CS
LL5R
= A0R – A12R
LL5R
= A0L – A12L
H
L
L–Port Wins
RL5L
= A0R – A12R
RL5L
= A0L – A12L
L
H
R–Port Wins
LW5R
= A0R – A12R
LW5R
= A0L – A12L
H
L
Arbitration Resolved
LW5R
= A0R – A12R
LW5R
= A0L – A12L
L
H
Arbitration Resolved
Notes :
1. INT Flags Don’t Care.
2. X = DON’T CARE, L = LOW, H = HIGH.
LV5R = Left Address Valid
≥ 5 ns before right address.
RV5L = Right Address Valid
≥ 5 ns before left address.
Same = Left and Right Addresses match within 5 ns of each other.
LL5R = Left CS = LOW
≥ 5 ns before Right CS.
RL5L = Right CS = LOW
≥ 5 ns before left CS.
LW5R = Left and Right CS = LOW within 5 ns of each other.
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