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參數(shù)資料
| 型號： | MMC2001HCAB33B |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 0K |
| 描述： | IC MCU 32BIT 33MHZ 144-LQFP |
| 標準包裝： | 60 |
| 系列： | MCore |
| 核心處理器： | M210 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 24 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 809 (CN2011-ZH PDF) |
4
MCORE ARCHITECTURAL INFORMATION
MOTOROLA
—
Assembly and disassembly of MCORE instructions for modification and display of code
—
Single-step trace and continued execution from a specified address
—
Modification, display, and movement of system memory
—
Setting, displaying, and removing breakpoints
—
Extensive on-line help
—
Ability to execute user-assembled and/or downloaded software in a controlled environment
—
Automatic decompression of compressed S-record files while downloading
—
Logging function for generating a transcript of a debugging session
EXTERNAL INTERFACE MODULE
The EIM provides 20 address lines and 16 data lines. It supports aligned byte, halfword, and word transfers
via 8-bit and 16-bit ports. The upper or lower byte of the data bus can be used for 8-bit transfers. The EIM
incorporates four chip-select circuits for external devices. Each chip select has a match address range of
16 mbytes, programmable wait state, selectable protection, and programmable data port size. Each unused
chip-select pin can be programmed four use as a general-purpose output. The EIM also includes the logic
for external/internal Boot ROM select and a bus watchdog for all internal and external bus cycles. Show
cycles are available for external visibility of internal bus cycles.
CLOCK GENERATION MODULE
This module controls system clock signals and implements low-power operation. There are two system
clock signals. The HI_REFCLK signal for the processor is provided via an external clock input pin (CLKIN).
The LOW_REFCLK signal is driven by an external crystal oscillator connected to the VOSC, XOSX, and
EXOSC pins. On-chip peripherals can use LOW_REFCLK, HI_REFCLK, a prescaled LOW_REFCLK, or a
combination of these, but must be properly synchronized when different clock sources are used. On-chip
peripherals can be shut down independently of the processor. The CLKOUT pin can be driven by either
HI_REFCLK or LOW_REFCLK, or it can be de-activated.
There are four operating modes: RUN, WAIT, DOZE, STOP. Different output encodings on the LMPD pins
inform external devices which mode is in use. RUN mode is for normal full operation, with all system clocks
operating. The remaining modes are for power conservation; each has an associated CPU instruction.
All low power modes halt the CPU, which then must be awakened by an interrupt request or a reset. The
TOD timer is unaffected by any low-power mode. In WAIT mode, only the CPU is halted, and it can be wak-
ened by any interrupt request. Individual on-chip peripherals are pre-programmed for DOZE operation;
some shut down, while some remain active. Peripherals that remain active can generate interrupt requests
and wake up the CPU. In STOP mode, most system clocks are halted, but the programmable interrupt and
watchdog timers can be used to wake up the system (both can also be stopped). Most on-chip peripherals
retain control register values during STOP mode, but peripheral operations must be properly terminated be-
fore STOP in order to assure orderly re-activation when normal mode operation resumes.
TIMER/RESET MODULE
The Timer/Reset module contains four timer sub-modules and the device reset control logic. The reset logic
provides reset source status and controls the CLKOUT pin. There are four possible sources of system reset
(Low-voltage monitor signal, external reset signal, power-on, and watchdog); there is a status bit for each
of the reset sources. The CLKOUT signal is disabled during reset, to assure proper synchronization of ex-
ternal devices that use it as a clock reference. It must be re-enabled as a part of system initialization.
Timer functions include:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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