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參數資料
| 型號： | MMC2001HCAB33B |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 33MHZ 144-LQFP |
| 標準包裝： | 60 |
| 系列： | MCore |
| 核心處理器： | M210 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數： | 24 |
| 程序存儲器容量： | 256KB（256K x 8） |
| 程序存儲器類型： | ROM |
| RAM 容量： | 32K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 144-LQFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 809 (CN2011-ZH PDF) |
MOTOROLA
MMC2001 PRODUCT INFORMATION
3
Sixteen general purpose registers are provided for source operands and instruction results. Register R15 is
used as the Link Register to hold the return address for subroutine calls and Register R0 is used as the current
Stack Pointer by convention.
The execution unit consists of a 32-bit Arithmetic/Logic Unit (ALU), a 32-bit Barrel Shifter (Shifter), Find-First-
One unit (FFO), Result Feed-Forward hardware, and miscellaneous support hardware for multiplication,
division, and multiple register load and stores. Arithmetic and Logical operations are executed in a single cycle
with the exception of multiply and divide. Multiply is implemented with a 2-bit per clock, overlapped-scan,
modified Booth algorithm with early-out capability to reduce execution time for operations with small
multipliers. Divide is implemented with a 1-bit per clock early-in algorithm. The Find-First-One unit operates in
a single clock cycle.
The Program Counter Unit has a PC incrementer and a dedicated Branch Address Adder to minimize delays
during change of flow operations. Branch target addresses are calculated in parallel with branch instruction
decode, with a single pipeline bubble for taken branches and jumps, resulting in an execution time of two
clocks. Conditional Branches which are not taken execute in a single clock.
Memory load and store operations are provided for byte, halfword and word (32-bit) data with automatic zero
extension of byte and halfword load data. These instructions can execute in two clock cycles. Load and store
multiple register instructions allow low overhead context save and restore operations; these instructions can
execute in (N+1) clock cycles, where N is the number of registers to transfer.
A single Condition/Code Carry (C) bit is provided for condition testing and for use in implementing arithmetic
and logical operations greater than 32-bits. Typically, the C bit is set only by explicit test/comparison
operations, not as a side-effect of normal instruction operation. Exceptions to this rule occur for specialized
operations where it is desirable to combine condition setting with actual computation.
A 16-entry Alternate register file is provided to support low overhead interrupt exception processing, and both
vectored and autovectored interrupts are supported by the CPU.
DEBUG INTERFACE
The MCORE architecture includes on-chip emulation (OnCE) circuitry. A JTAG interface provides the means
of interacting with the MCORE processor and on-chip peripherals. A user can examine processor and on-chip
peripheral registers, memory, and instruction execution to facilitate hardware/software development. Debug
status and control registers are accessible during OnCE operation. Special circuitry and interface pins are
provided to support non-intrusive debug and efficient use of on-chip resources.
INTERNAL STANDBY RAM
The 32 kbyte on-chip SRAM supports single-clock access by the MCORE processor. SRAM supports byte,
half-word and word accesses. The RAM array is divided into two separate blocks that can be independently
activated in order to conserve power.
ON-CHIP ROM
The 256-kbyte ROM is pre-programmed with development support code, including.
Floating Point Routines
—
MCORE ABI compliant routines to implement floating-point computation
MBUG
Motorola Monitor Debugger program with the following features:
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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