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參數(shù)資料
| 型號： | MM58167MWC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, UUC24 |
| 封裝： | WAFER-24 |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 195K |
| 代理商： | MM58167MWC |
Functional Description (Continued)
Typical Supply Current
vs Supply Voltage
Standby Interrupt
during Power Down
Typical Characteristics
TLF11070 – 4
TLF11070 – 5
FIGURE 2
Interrupt Timing 0 C s TA s 70 C 45V s VDD s 55V VSS e 0V
Symbol
Parameter
Min
Max
Units
tINTON
Status Register Clock to INTERRUPT OUTPUT
5
m
s
(Pin 13) High (Note 1)
tSBYON
Compare Valid to STANDBY INTERRUPT
5
m
s
(Pin 14) Low (Note 1)
tINTOFF
Trailing Edge of Status Register
5
m
s
Read to INTERRUPT OUTPUT Low
tSBYOFF
Trailing Edge of Write Cycle
(D0 e 0 Address e 16H) to STANDBY
5
m
s
INTERRUPT Off (High Impedance State)
Note 1
The status register clocks are the corresponding counter’s rollover to its reset state or the compare becoming valid The compare becomes valid 61 ms
after the 110000 of a second counter is clocked if the real time counter data matches the RAM data
Read Cycle Timing 0 C s TA s 70 C 45V s VDD s 55V VSS e 0V
Symbol
Parameter
Min
Max
Units
tAR
Address Bus Valid to Read Strobe (Note 3)
100
ns
tCSR
Chip Select to Read Strobe (Note 2)
0
ns
tRRY
Read Strobe to Ready Strobe
150
ns
tRYD
Ready Strobe to Data Valid
800
ns
tAD
Address Bus Valid to Data Valid
1050
ns
tRH
Data Hold Time from Trailing Edge of Read Strobe
0
ns
tHZ
Trailing Edge of Read Strobe to TRI-STATE Mode
250
ns
tRYH
Read Hold Time after Ready Strobe
0
ns
tRA
Address Bus Hold Time from Trailing Edge of Read Strobe
50
ns
tRYDV
Rising Edge of Ready to Data Valid
100
ns
Note 2
When reading a deselect time of 500 ns minimum must occur between counter reads Deselect is CS e 1or(WR)
(RD) e 1
Note 3
If tAR e 0 and Chip Select Address Valid or Read are coincident then they must exist for 1050 ns
6
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